[MSDK-976] Removed PUF references from ME18. (#318)

* MSDK-976: Removed PUF references from ME18.

* ME18: Added owm_reva_me18.svd to reflect correct CTRL_STAT.presence_detect (bit 5) position.

* ME18: Removed PUF keys from AESKEYS.

* Verify_Register_SVD: Updated the action to pass if an unsupported file was deleted.

---------

Co-authored-by: Eddie <[email protected]>
MSDK-Commit: e7b885bd75e2c0425fb00578889d31a4e582a811

Author: 2 people

MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/aeskeys_regs.h

@@ -88,8 +88,6 @@ extern "C" {
 typedef struct {
     __IO uint128_t key0;                 /**< <tt>\b 0x000:</tt> AESKEYS KEY0 Register */
     __IO uint128_t key1;                 /**< <tt>\b 0x010:</tt> AESKEYS KEY1 Register */
-    __IO uint256_t puf_key1;             /**< <tt>\b 0x020:</tt> AESKEYS PUF_KEY1 Register */
-    __IO uint256_t puf_key2;             /**< <tt>\b 0x040:</tt> AESKEYS PUF_KEY2 Register */
 } mxc_aeskeys_regs_t;
 
 /* Register offsets for module AESKEYS */
@@ -101,8 +99,6 @@ typedef struct {
  */
 #define MXC_R_AESKEYS_KEY0                 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS Base Address: <tt> 0x0000</tt> */
 #define MXC_R_AESKEYS_KEY1                 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS Base Address: <tt> 0x0010</tt> */
-#define MXC_R_AESKEYS_PUF_KEY1             ((uint32_t)0x00000020UL) /**< Offset from AESKEYS Base Address: <tt> 0x0020</tt> */
-#define MXC_R_AESKEYS_PUF_KEY2             ((uint32_t)0x00000040UL) /**< Offset from AESKEYS Base Address: <tt> 0x0040</tt> */
 /**@} end of group aeskeys_registers */
 
 #ifdef __cplusplus

MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.h

@@ -174,7 +174,7 @@ typedef enum {
     RSV92_IRQn, /* 0x6C  0x01B0 108: Reserved */
     RSV93_IRQn, /* 0x6D  0x01B4 109: Reserved */
     RSV94_IRQn, /* 0x6E  0x01B8 110: Reserved */
-    PUF_IRQn, /* 0x6F  0x01BC 111: Physically Uncloneable Function */
+    RSV95_IRQn, /* 0x6F  0x01BC 111: Reserved */
     RSV96_IRQn, /* 0x70  0x01C0 112: Reserved */
     RSV97_IRQn, /* 0x71  0x01C4 113: Reserved */
     RSV98_IRQn, /* 0x72  0x01C8 114: Reserved */
@@ -394,11 +394,6 @@ typedef enum {
 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL)
 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR)
 
-/******************************************************************************/
-/*                                                     PUF Secure Controller  */
-#define MXC_BASE_PUF ((uint32_t)0x40007000UL)
-#define MXC_PUF ((mxc_puf_regs_t *)MXC_BASE_PUF)
-
 /******************************************************************************/
 /*                                                                       GPIO */
 #define MXC_CFG_GPIO_INSTANCES (5)