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lines changed Original file line number Diff line number Diff line change @@ -11,9 +11,25 @@ config BOARD
1111
1212choice CODE_LOCATION
1313 default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7
14+ default CODE_OCRAM if BOARD_MIMXRT1160_EVK_CM4 && SECOND_CORE_MCUX
1415 default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4
1516endchoice
1617
18+ if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_CM4
19+
20+ config BUILD_OUTPUT_INFO_HEADER
21+ default y
22+
23+ DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
24+
25+ # Adjust the offset of the output image if building for RT11xx SOC
26+ config BUILD_OUTPUT_ADJUST_LMA
27+ default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
28+ $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
29+ $(dt_node_reg_addr_hex,/soc/ocram@20200000)"
30+
31+ endif
32+
1733config SYS_CLOCK_HW_CYCLES_PER_SEC
1834 default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK
1935 default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK
Original file line number Diff line number Diff line change 44# SPDX-License-Identifier: Apache-2.0
55#
66
7- if (CONFIG_SOC_MIMXRT1166_CM7)
7+ if (CONFIG_SOC_MIMXRT1166_CM7 OR CONFIG_SECOND_CORE_MCUX )
88board_runner_args(pyocd "--target=mimxrt1160_cm7" )
99board_runner_args(jlink "--device=MIMXRT1166xxx6_M7" "--reset-after-load" )
10- endif ()
11-
12- if (CONFIG_SOC_MIMXRT1166_CM4)
10+ elseif (CONFIG_SOC_MIMXRT1166_CM4)
1311board_runner_args(pyocd "--target=mimxrt1160_cm4" )
1412# Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
1513board_runner_args(jlink "--device=MIMXRT1166xxx6_M4" )
Original file line number Diff line number Diff line change 2525 zephyr,shell-uart = &lpuart1;
2626 zephyr,flash-controller = &is25wp128;
2727 zephyr,flash = &is25wp128;
28+ nxp,m4-partition = &slot1_partition;
2829 };
2930
3031
Original file line number Diff line number Diff line change 2323 zephyr,flash-controller = &is25wp128;
2424 zephyr,flash = &is25wp128;
2525 zephyr,code-partition = &slot0_partition;
26+ zephyr,cpu1-region = &ocram;
2627 };
2728
2829 sdram0: memory@80000000 {
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