riscv vector ISA support

[rjiejie]

@paulfloyd @petrpavlu
We consider to add RVV/Vector feature in valgrind and met some issues from investigation.

RVV like ARM's SVE programming model, it's scalable/VLA, that means the vector length is agnostic.
ARM's SVE is not supported in valgrind :(

There is not any VLA vector IR to represent these vector model, it's the big issue.
Also some other common module like "register allocator" in VEX can not represent vector type which use
more than one register.
In another hand, some tool plugin like Memcheck will use data type like "Ity_V128/Ity_V256" to generate IRs, it's a big challenge

Any ideas for supporting of scalable vector model ?

[petrpavlu]

Apologies for the lack of a response. I've started looking at the vector extension to get some understanding what could be done but need to spend more time to chew on it all.

[rjiejie]

FYI, intel's AVX-512 [1] met some common issues like RVV or ARM's SVE.
you could consider that how to fix that also although it is SIMD model.
BTW, Julian Seward take some efforts in AVX-512, maybe we could invite him in RVV design :)
and append our RVV RFC [2] in valgrind mail list below.

[1] https://bugs.kde.org/show_bug.cgi?id=383010
[2] https://sourceforge.net/p/valgrind/mailman/message/37834524/

[rjiejie]

Any progress about this feature ?
@petrpavlu @paulfloyd

[rjiejie]

Hi,

We are glad to open source RVV implementation here:

https://github.com/rjiejie/valgrind-riscv64

4 kinds extra ISAs were added in this repo:

RV64Zfh : Half-precision floating-point
RV64Xthead [1] : T-HEAD vendor extension for RV64G
RV64V0p7 [2] : Vector 0.7.1
RV64V [3] : Vector 1.0

[1] https://github.com/T-head-Semi/thead-extension-spec
[2] https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1
[3] https://github.com/riscv/riscv-v-spec/releases/tag/v1.0