@@ -9,11 +9,13 @@ def __init__(self, logfile, start, size):
99 self .end = start + size - 1
1010 self ._mem = numpy .zeros (size , dtype = numpy .uint8 )
1111
12- def load (self , address , data ):
13- for offset , datum in enumerate (data ):
14- self ._mem [address - self .start + offset ] = datum
12+ def load_bin (self , address , filename ):
13+ with open (filename , "rb" ) as f :
14+ data = f .read ()
15+ for offset , datum in enumerate (data ):
16+ self ._mem [address - self .start + offset ] = datum
1517
16- def load_file (self , address , filename ):
18+ def init_bin (self , address , filename ):
1719 with open (filename , "rb" ) as f :
1820 self ._mem = numpy .fromfile (f , dtype = numpy .uint8 )
1921
@@ -62,7 +64,6 @@ def read_byte(self, cycle, address):
6264 pass # print "%04X" % address
6365 return 0x00
6466
65-
6667class Memory :
6768 def __init__ (self , options , display = None ):
6869 self .display = display
@@ -75,20 +76,18 @@ def __init__(self, options, display=None):
7576
7677 self .ram = RAM (self .logfile , 0x0000 , 0xC000 )
7778 self .rom = ROM (self .logfile , 0xD000 , 0x3000 )
78- self .rom .load_file (0xD000 , self .options .rom )
79+ self .rom .init_bin (0xD000 , self .options .rom )
7980
80- if self .options .load :
81- ih = IntelHex (self .options .load )
81+ if self .options .hex :
82+ ih = IntelHex (self .options .hex )
8283 d = ih .todict ()
8384 for addr , v in d .items ():
8485 self .write_byte (addr , v )
86+ elif self .options .bin and self .options .addr :
87+ self .ram .load_bin (self .options .addr , self .options .bin )
8588
8689 self .softswitches = SoftSwitches (display )
8790
88- # def load(self, address, data):
89- # if address < 0xC000:
90- # self.ram.load(address, data)
91-
9291 def read_byte (self , cycle , address ):
9392 if address < 0xC000 :
9493 return self .ram .read_byte (address )
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