Skip to content

Commit 0b79199

Browse files
committed
Peephole Code Optimization:
ldr + sxtw -> ldrsw lsl + add/sub/cmp -> add/sub/cmp (shifted register) LOAD_64BIT_VAL + add -> ADD_SUB_64_WITH_CONST
1 parent 00270c6 commit 0b79199

File tree

1 file changed

+21
-23
lines changed

1 file changed

+21
-23
lines changed

ext/opcache/jit/zend_jit_arm64.dasc

Lines changed: 21 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -670,6 +670,16 @@ static int logical_immediate_p (uint64_t value, uint32_t reg_size)
670670
|| }
671671
|.endmacro
672672

673+
|.macro ADD_IP_SHIFT, val, shift, tmp_reg
674+
|| if (GCC_GLOBAL_REGS) {
675+
| add IP, IP, val, shift
676+
|| } else {
677+
| ldr tmp_reg, EX->opline
678+
| add tmp_reg, tmp_reg, val, shift
679+
| str tmp_reg, EX->opline
680+
|| }
681+
|.endmacro
682+
673683
|.macro ADD_IP_FROM_CST, val, tmp_reg
674684
|| ZEND_ASSERT(val >=0 && val <= ADD_SUB_IMM);
675685
|| if (GCC_GLOBAL_REGS) {
@@ -1926,8 +1936,7 @@ static int zend_jit_undefined_offset_stub(dasm_State **Dst)
19261936
| ldrb REG1w, OP:REG0->op2_type
19271937
| cmp REG1w, #IS_CONST
19281938
| bne >2
1929-
| ldr REG1w, OP:REG0->op2.constant
1930-
| sxtw REG1, REG1w
1939+
| ldrsw REG1, OP:REG0->op2.constant
19311940
| add REG0, REG0, REG1
19321941
| b >3
19331942
|2:
@@ -1964,8 +1973,7 @@ static int zend_jit_undefined_index_stub(dasm_State **Dst)
19641973
| ldrb REG1w, OP:REG0->op2_type
19651974
| cmp REG1w, #IS_CONST
19661975
| bne >2
1967-
| ldr REG1w, OP:REG0->op2.constant
1968-
| sxtw REG1, REG1w
1976+
| ldrsw REG1, OP:REG0->op2.constant
19691977
| add REG0, REG0, REG1
19701978
| b >3
19711979
|2:
@@ -2019,8 +2027,7 @@ static int zend_jit_undefined_function_stub(dasm_State **Dst)
20192027
| ldr REG0, EX->opline
20202028
| mov CARG1, xzr
20212029
| LOAD_ADDR CARG2, "Call to undefined function %s()"
2022-
| ldr CARG3w, [REG0, #offsetof(zend_op, op2.constant)]
2023-
| sxtw CARG3, CARG3w
2030+
| ldrsw CARG3, [REG0, #offsetof(zend_op, op2.constant)]
20242031
| ldr CARG3, [REG0, CARG3]
20252032
| add CARG3, CARG3, #offsetof(zend_string, val)
20262033
| EXT_CALL zend_throw_error, REG0
@@ -4939,14 +4946,11 @@ static int zend_jit_fetch_dimension_address_inner(dasm_State **Dst, const zend_o
49394946
if (val >= 0) {
49404947
| ldr REG0, [FCARG1x, #offsetof(zend_array, arData)]
49414948
if (val != 0) {
4942-
| LOAD_64BIT_VAL TMP1, val * sizeof(Bucket)
4943-
| add REG0, REG0, TMP1
4949+
| ADD_SUB_64_WITH_CONST add, REG0, REG0, (val * sizeof(Bucket)), TMP1
49444950
}
49454951
} else {
4946-
| mov REG0, FCARG2x
4947-
| lsl REG0, REG0, #5
49484952
| ldr TMP1, [FCARG1x, #offsetof(zend_array, arData)]
4949-
| add REG0, REG0, TMP1
4953+
| add REG0, TMP1, FCARG2x, lsl #5
49504954
}
49514955
}
49524956
}
@@ -8257,9 +8261,8 @@ static int zend_jit_push_call_frame(dasm_State **Dst, const zend_op *opline, con
82578261
| ldr TMP1w, [REG0, #offsetof(zend_closure, func.op_array.T)]
82588262
| sub REG2w, REG2w, TMP1w
82598263
}
8260-
| lsl REG2w, REG2w, #5
82618264
| sxtw REG2, REG2w
8262-
| sub FCARG1x, FCARG1x, REG2
8265+
| sub FCARG1x, FCARG1x, REG2, lsl #5
82638266
|1:
82648267
}
82658268

@@ -9469,8 +9472,7 @@ static int zend_jit_do_fcall(dasm_State **Dst, const zend_op *opline, const zend
94699472
| // opline += num_args;
94709473
|| ZEND_ASSERT(sizeof(zend_op) == 32);
94719474
| mov REG2w, REG1w
9472-
| lsl REG2, REG2, #5
9473-
| ADD_IP REG2, TMP1
9475+
| ADD_IP_SHIFT REG2, lsl #5, TMP1
94749476
}
94759477
|1:
94769478
| // if (EXPECTED((int)num_args < op_array->last_var)) {
@@ -9482,8 +9484,7 @@ static int zend_jit_do_fcall(dasm_State **Dst, const zend_op *opline, const zend
94829484
| subs REG2w, REG2w, REG1w
94839485
| ble >3
94849486
| // zval *var = EX_VAR_NUM(num_args);
9485-
| lsl REG1, REG1, #4
9486-
| add REG1, REG1, FP
9487+
| add REG1, FP, REG1, lsl #4
94879488
|| ZEND_ASSERT(ZEND_CALL_FRAME_SLOT * sizeof(zval) <= ADD_SUB_IMM);
94889489
| add REG1, REG1, #(ZEND_CALL_FRAME_SLOT * sizeof(zval))
94899490
|2:
@@ -11783,8 +11784,7 @@ static int zend_jit_bind_global(dasm_State **Dst, const zend_op *opline, uint32_
1178311784
| sub REG0, REG0, #1
1178411785
| // if (EXPECTED(idx < EG(symbol_table).nNumUsed * sizeof(Bucket)))
1178511786
| MEM_LOAD_32_ZTS ldr, REG1w, executor_globals, symbol_table.nNumUsed, REG1
11786-
| lsl REG1, REG1, #5
11787-
| cmp REG0, REG1
11787+
| cmp REG0, REG1, lsl #5
1178811788
| bhs >9
1178911789
| // Bucket *p = (Bucket*)((char*)EG(symbol_table).arData + idx);
1179011790
| MEM_LOAD_ZTS ldr, TMP1, executor_globals, symbol_table.arData, REG1
@@ -13791,8 +13791,7 @@ static int zend_jit_switch(dasm_State **Dst, const zend_op *opline, const zend_o
1379113791
| bhs =>default_b
1379213792
}
1379313793
| adr REG0, >4
13794-
| lsl TMP1, FCARG2x, #3
13795-
| ldr TMP1, [REG0, TMP1]
13794+
| ldr TMP1, [REG0, FCARG2x, lsl #3]
1379613795
| br TMP1
1379713796

1379813797
|.jmp_table
@@ -14132,9 +14131,8 @@ static int zend_jit_fe_fetch(dasm_State **Dst, const zend_op *opline, uint32_t o
1413214131
| // p = fe_ht->arData + pos;
1413314132
|| ZEND_ASSERT(sizeof(Bucket) == 32);
1413414133
| mov FCARG2w, REG0w
14135-
| lsl FCARG2x, FCARG2x, #5
1413614134
| ldr TMP1, [FCARG1x, #offsetof(zend_array, arData)]
14137-
| add FCARG2x, FCARG2x, TMP1
14135+
| add FCARG2x, TMP1, FCARG2x, lsl #5
1413814136
|1:
1413914137
| // if (UNEXPECTED(pos >= fe_ht->nNumUsed)) {
1414014138
| ldr TMP1w, [FCARG1x, #offsetof(zend_array, nNumUsed)]

0 commit comments

Comments
 (0)