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arnaud-lbarnaud-lb
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Alternative tailcall fix
1 parent 103a5e8 commit a659661

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3 files changed

+127
-96
lines changed

3 files changed

+127
-96
lines changed

‎ext/opcache/jit/ir/ir_ra.c‎

Lines changed: 41 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -610,8 +610,8 @@ int ir_compute_live_ranges(ir_ctx *ctx)
610610
len = ir_bitset_len(ctx->vregs_count + 1);
611611
bb_live = ir_mem_malloc((ctx->cfg_blocks_count + 1) * len * sizeof(ir_bitset_base_t));
612612

613-
/* vregs + tmp + fixed + SRATCH + ALL */
614-
ctx->live_intervals = ir_mem_calloc(ctx->vregs_count + 1 + IR_REG_NUM + 2, sizeof(ir_live_interval*));
613+
/* vregs + tmp + fixed + special */
614+
ctx->live_intervals = ir_mem_calloc(ctx->vregs_count + 1 + IR_REG_NUM + IR_REG_SPECIAL_NUM, sizeof(ir_live_interval*));
615615

616616
#ifdef IR_DEBUG
617617
visited = ir_bitset_malloc(ctx->cfg_blocks_count + 1);
@@ -1262,8 +1262,8 @@ int ir_compute_live_ranges(ir_ctx *ctx)
12621262
/* Compute Live Ranges */
12631263
ctx->flags2 &= ~IR_LR_HAVE_DESSA_MOVES;
12641264

1265-
/* vregs + tmp + fixed + SRATCH + ALL */
1266-
ctx->live_intervals = ir_mem_calloc(ctx->vregs_count + 1 + IR_REG_NUM + 2, sizeof(ir_live_interval*));
1265+
/* vregs + tmp + fixed + special */
1266+
ctx->live_intervals = ir_mem_calloc(ctx->vregs_count + 1 + IR_REG_NUM + IR_REG_SPECIAL_NUM, sizeof(ir_live_interval*));
12671267

12681268
if (!ctx->arena) {
12691269
ctx->arena = ir_arena_create(16 * 1024);
@@ -2036,8 +2036,8 @@ int ir_coalesce(ir_ctx *ctx)
20362036
n--;
20372037
if (n != ctx->vregs_count) {
20382038
j = ctx->vregs_count - n;
2039-
/* vregs + tmp + fixed + SRATCH + ALL */
2040-
for (i = n + 1; i <= n + IR_REG_NUM + 2; i++) {
2039+
/* vregs + tmp + fixed + special */
2040+
for (i = n + 1; i <= n + IR_REG_NUM + IR_REG_SPECIAL_NUM; i++) {
20412041
ctx->live_intervals[i] = ctx->live_intervals[i + j];
20422042
if (ctx->live_intervals[i]) {
20432043
ctx->live_intervals[i]->vreg = i;
@@ -2804,6 +2804,35 @@ static void ir_add_to_unhandled_spill(ir_live_interval **unhandled, ir_live_inte
28042804
}
28052805
}
28062806

2807+
static ir_regset ir_special_reg_regset(ir_ctx *ctx, uint8_t reg)
2808+
{
2809+
IR_ASSERT(reg >= IR_REG_SCRATCH);
2810+
2811+
switch (reg) {
2812+
case IR_REG_SCRATCH:
2813+
return IR_REGSET_SCRATCH;
2814+
case IR_REG_PRESERVED:
2815+
return IR_REGSET_PRESERVED;
2816+
case IR_REG_FIXED_SAVED:
2817+
IR_ASSERT(ctx->fixed_stack_frame_size != -1);
2818+
return (ir_regset)ctx->fixed_save_regset;
2819+
case IR_REG_ARGS:
2820+
return IR_REGSET_ARGS;
2821+
#ifdef IR_HAVE_FASTCALL
2822+
case IR_REG_FCARGS:
2823+
return IR_REGSET_FCARGS;
2824+
#endif
2825+
#ifdef IR_HAVE_PRESERVE_NONE
2826+
case IR_REG_PNARGS:
2827+
return IR_REGSET_PNARGS;
2828+
#endif
2829+
case IR_REG_ALL:
2830+
return ~0;
2831+
default:
2832+
IR_ASSERT(0);
2833+
}
2834+
}
2835+
28072836
static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_live_interval **active, ir_live_interval *inactive, ir_live_interval **unhandled)
28082837
{
28092838
ir_live_pos freeUntilPos[IR_REG_NUM];
@@ -2846,12 +2875,7 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
28462875
reg = other->reg;
28472876
IR_ASSERT(reg >= 0);
28482877
if (reg >= IR_REG_SCRATCH) {
2849-
if (reg == IR_REG_SCRATCH) {
2850-
available = IR_REGSET_DIFFERENCE(available, IR_REGSET_SCRATCH);
2851-
} else {
2852-
IR_ASSERT(reg == IR_REG_ALL);
2853-
available = IR_REGSET_EMPTY;
2854-
}
2878+
available = IR_REGSET_DIFFERENCE(available, ir_special_reg_regset(ctx, reg));
28552879
} else {
28562880
IR_REGSET_EXCL(available, reg);
28572881
}
@@ -2874,14 +2898,8 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
28742898
reg = other->reg;
28752899
IR_ASSERT(reg >= 0);
28762900
if (reg >= IR_REG_SCRATCH) {
2877-
ir_regset regset;
2901+
ir_regset regset = IR_REGSET_INTERSECTION(available, ir_special_reg_regset(ctx, reg));
28782902

2879-
if (reg == IR_REG_SCRATCH) {
2880-
regset = IR_REGSET_INTERSECTION(available, IR_REGSET_SCRATCH);
2881-
} else {
2882-
IR_ASSERT(reg == IR_REG_ALL);
2883-
regset = available;
2884-
}
28852903
overlapped = IR_REGSET_UNION(overlapped, regset);
28862904
IR_REGSET_FOREACH(regset, reg) {
28872905
if (next < freeUntilPos[reg]) {
@@ -3087,14 +3105,8 @@ static ir_reg ir_allocate_blocked_reg(ir_ctx *ctx, ir_live_interval *ival, ir_li
30873105
reg = other->reg;
30883106
IR_ASSERT(reg >= 0);
30893107
if (reg >= IR_REG_SCRATCH) {
3090-
ir_regset regset;
3108+
ir_regset regset = IR_REGSET_INTERSECTION(available, ir_special_reg_regset(ctx, reg));
30913109

3092-
if (reg == IR_REG_SCRATCH) {
3093-
regset = IR_REGSET_INTERSECTION(available, IR_REGSET_SCRATCH);
3094-
} else {
3095-
IR_ASSERT(reg == IR_REG_ALL);
3096-
regset = available;
3097-
}
30983110
IR_REGSET_FOREACH(regset, reg) {
30993111
blockPos[reg] = nextUsePos[reg] = 0;
31003112
} IR_REGSET_FOREACH_END();
@@ -3122,14 +3134,8 @@ static ir_reg ir_allocate_blocked_reg(ir_ctx *ctx, ir_live_interval *ival, ir_li
31223134
ir_live_pos overlap = ir_ivals_overlap(&ival->range, other->current_range);
31233135

31243136
if (overlap) {
3125-
ir_regset regset;
3137+
ir_regset regset = IR_REGSET_INTERSECTION(available, ir_special_reg_regset(ctx, reg));
31263138

3127-
if (reg == IR_REG_SCRATCH) {
3128-
regset = IR_REGSET_INTERSECTION(available, IR_REGSET_SCRATCH);
3129-
} else {
3130-
IR_ASSERT(reg == IR_REG_ALL);
3131-
regset = available;
3132-
}
31333139
IR_REGSET_FOREACH(regset, reg) {
31343140
if (overlap < nextUsePos[reg]) {
31353141
nextUsePos[reg] = overlap;
@@ -3562,8 +3568,8 @@ static int ir_linear_scan(ir_ctx *ctx)
35623568
ir_merge_to_unhandled(&unhandled, ival);
35633569
}
35643570

3565-
/* vregs + tmp + fixed + SRATCH + ALL */
3566-
for (j = ctx->vregs_count + 1; j <= ctx->vregs_count + IR_REG_NUM + 2; j++) {
3571+
/* vregs + tmp + fixed + special */
3572+
for (j = ctx->vregs_count + 1; j <= ctx->vregs_count + IR_REG_NUM + IR_REG_SPECIAL_NUM; j++) {
35673573
ival = ctx->live_intervals[j];
35683574
if (ival) {
35693575
ival->current_range = &ival->range;

‎ext/opcache/jit/ir/ir_x86.dasc‎

Lines changed: 61 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -1415,8 +1415,6 @@ op2_const:
14151415
}
14161416
constraints->tmp_regs[0] = IR_SCRATCH_REG(IR_REG_SCRATCH, IR_USE_SUB_REF, IR_DEF_SUB_REF);
14171417
n = 1;
1418-
IR_FALLTHROUGH;
1419-
case IR_TAILCALL:
14201418
insn = &ctx->ir_base[ref];
14211419
if (insn->inputs_count > 2) {
14221420
constraints->hints[2] = IR_REG_NONE;
@@ -1428,6 +1426,43 @@ op2_const:
14281426
}
14291427
flags = IR_USE_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG | IR_OP3_SHOULD_BE_IN_REG;
14301428
break;
1429+
case IR_TAILCALL:
1430+
insn = &ctx->ir_base[ref];
1431+
/* For TAILCALL we don't need to reserve all scratch registers. */
1432+
uint8_t args = IR_REG_ARGS;
1433+
uint8_t tmp_reg = IR_REG_INT_RET1;
1434+
#ifdef IR_HAVE_FASTCALL
1435+
if (ir_is_fastcall(ctx, insn)) {
1436+
args = IR_REG_FCARGS;
1437+
}
1438+
#endif
1439+
#ifdef IR_HAVE_PRESERVE_NONE
1440+
if (ir_is_preserve_none(ctx, insn)) {
1441+
args = IR_REG_PNARGS;
1442+
tmp_reg = IR_REG_R10;
1443+
}
1444+
#endif
1445+
constraints->tmp_regs[n] = IR_SCRATCH_REG(args, IR_USE_SUB_REF, IR_DEF_SUB_REF);
1446+
n++;
1447+
/* Reserve tmp register used by ir_emit_arguments() */
1448+
constraints->tmp_regs[n] = IR_SCRATCH_REG(tmp_reg, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
1449+
n++;
1450+
if (!IR_IS_CONST_REF(insn->op2)) {
1451+
uint8_t preserved;
1452+
if (ctx->fixed_stack_frame_size != -1) {
1453+
preserved = IR_REG_FIXED_SAVED;
1454+
} else {
1455+
preserved = IR_REG_PRESERVED;
1456+
}
1457+
constraints->tmp_regs[n] = IR_SCRATCH_REG(preserved, IR_USE_SUB_REF, IR_DEF_SUB_REF);
1458+
n++;
1459+
}
1460+
if (insn->inputs_count > 2) {
1461+
constraints->hints[2] = IR_REG_NONE;
1462+
constraints->hints_count = ir_get_args_regs(ctx, insn, constraints->hints);
1463+
}
1464+
flags = IR_USE_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG | IR_OP3_SHOULD_BE_IN_REG | IR_DEF_CONFLICTS_WITH_INPUT_REGS;
1465+
break;
14311466
case IR_BINOP_SSE2:
14321467
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG | IR_OP1_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG;
14331468
break;
@@ -9245,66 +9280,24 @@ static void ir_emit_tailcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
92459280
{
92469281
ir_backend_data *data = ctx->data;
92479282
dasm_State **Dst = &data->dasm_state;
9248-
int32_t used_stack = ir_emit_arguments(ctx, def, insn, ctx->regs[def][1]);
9283+
9284+
uint8_t tmp_reg = IR_REG_INT_RET1;
9285+
#ifdef IR_HAVE_PRESERVE_NONE
9286+
if (ir_is_preserve_none(ctx, insn)) {
9287+
/* preserve_none uses IR_REG_INT_RET1 for argument passing, so we can
9288+
* not use as tmp reg here. */
9289+
tmp_reg = IR_REG_R10;
9290+
}
9291+
#endif
9292+
9293+
int32_t used_stack = ir_emit_arguments(ctx, def, insn, tmp_reg);
92499294

92509295
if (used_stack != 0) {
92519296
ir_emit_call_ex(ctx, def, insn, used_stack);
92529297
ir_emit_return_void(ctx);
92539298
return;
92549299
}
92559300

9256-
/* Move op2 to a scratch register before epilogue if it's in
9257-
* used_preserved_regs, because it will be overridden. */
9258-
9259-
ir_reg op2_reg = IR_REG_NONE;
9260-
ir_mem mem = IR_MEM_B(IR_REG_NONE);
9261-
if (!IR_IS_CONST_REF(insn->op2)) {
9262-
op2_reg = ctx->regs[def][2];
9263-
9264-
if (op2_reg != IR_REG_NONE) {
9265-
if (IR_REG_SPILLED(op2_reg)) {
9266-
ZEND_ASSERT(0 && "TODO");
9267-
op2_reg = IR_REG_NUM(op2_reg);
9268-
ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
9269-
}
9270-
if (IR_REGSET_IN((ir_regset)ctx->used_preserved_regs, op2_reg)) {
9271-
ir_reg tmp_reg;
9272-
if (ir_is_preserve_none(ctx, insn)) {
9273-
tmp_reg = IR_REG_R10;
9274-
} else {
9275-
tmp_reg = IR_REG_INT_RET1;
9276-
}
9277-
9278-
| mov Rq(tmp_reg), Rq(op2_reg)
9279-
9280-
op2_reg = tmp_reg;
9281-
}
9282-
} else {
9283-
if (ir_rule(ctx, insn->op2) & IR_FUSED) {
9284-
mem = ir_fuse_load(ctx, def, insn->op2);
9285-
} else {
9286-
mem = ir_ref_spill_slot(ctx, insn->op2);
9287-
}
9288-
ir_reg base = IR_MEM_BASE(mem);
9289-
ir_reg index = IR_MEM_INDEX(mem);
9290-
if ((base != IR_REG_NONE && IR_REGSET_IN((ir_regset)ctx->used_preserved_regs, base)) ||
9291-
(index != IR_REG_NONE && IR_REGSET_IN((ir_regset)ctx->used_preserved_regs, index))) {
9292-
ir_reg tmp_reg;
9293-
if (ir_is_preserve_none(ctx, insn)) {
9294-
tmp_reg = IR_REG_R10;
9295-
} else {
9296-
tmp_reg = IR_REG_INT_RET1;
9297-
}
9298-
9299-
ir_type type = ctx->ir_base[insn->op2].type;
9300-
9301-
| ASM_REG_MEM_OP, mov, type, tmp_reg, mem
9302-
9303-
op2_reg = tmp_reg;
9304-
}
9305-
}
9306-
}
9307-
93089301
ir_emit_epilogue(ctx);
93099302

93109303
if (IR_IS_CONST_REF(insn->op2)) {
@@ -9330,9 +9323,22 @@ static void ir_emit_tailcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
93309323
|.endif
93319324
}
93329325
} else {
9326+
ir_reg op2_reg = ctx->regs[def][2];
9327+
93339328
if (op2_reg != IR_REG_NONE) {
9329+
if (IR_REG_SPILLED(op2_reg)) {
9330+
op2_reg = IR_REG_NUM(op2_reg);
9331+
ir_emit_load(ctx, IR_ADDR, op2_reg, insn->op2);
9332+
}
93349333
| jmp Ra(op2_reg)
93359334
} else {
9335+
ir_mem mem;
9336+
9337+
if (ir_rule(ctx, insn->op2) & IR_FUSED) {
9338+
mem = ir_fuse_load(ctx, def, insn->op2);
9339+
} else {
9340+
mem = ir_ref_spill_slot(ctx, insn->op2);
9341+
}
93369342
| ASM_TMEM_OP jmp, aword, mem
93379343
}
93389344
}

‎ext/opcache/jit/ir/ir_x86.h‎

Lines changed: 25 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -84,12 +84,19 @@ enum _ir_reg {
8484
IR_REG_NUM,
8585
};
8686

87-
#define IR_REG_GP_FIRST IR_REG_R0
88-
#define IR_REG_FP_FIRST IR_REG_XMM0
89-
#define IR_REG_GP_LAST (IR_REG_FP_FIRST - 1)
90-
#define IR_REG_FP_LAST (IR_REG_NUM - 1)
91-
#define IR_REG_SCRATCH (IR_REG_NUM) /* special name for regset */
92-
#define IR_REG_ALL (IR_REG_NUM + 1) /* special name for regset */
87+
#define IR_REG_GP_FIRST IR_REG_R0
88+
#define IR_REG_FP_FIRST IR_REG_XMM0
89+
#define IR_REG_GP_LAST (IR_REG_FP_FIRST - 1)
90+
#define IR_REG_FP_LAST (IR_REG_NUM - 1)
91+
#define IR_REG_SCRATCH (IR_REG_NUM) /* special name for regset */
92+
#define IR_REG_ALL (IR_REG_NUM + 1) /* special name for regset */
93+
#define IR_REG_PRESERVED (IR_REG_NUM + 2) /* special name for IR_REGSET_PRESERVED */
94+
#define IR_REG_FIXED_SAVED (IR_REG_NUM + 3) /* special name for fixed_save_regset */
95+
#define IR_REG_ARGS (IR_REG_NUM + 4) /* special name for IR_REGSET_ARGS */
96+
#define IR_REG_FCARGS (IR_REG_NUM + 5) /* special name for IR_REGSET_FCARGS */
97+
#define IR_REG_PNARGS (IR_REG_NUM + 6) /* special name for IR_REGSET_PNARGS */
98+
99+
#define IR_REG_SPECIAL_NUM 7
93100

94101
#define IR_REGSET_64BIT 0
95102

@@ -177,6 +184,11 @@ enum _ir_reg {
177184
| IR_REGSET(IR_REG_RBP) \
178185
| IR_REGSET_INTERVAL(IR_REG_R12, IR_REG_R15))
179186

187+
# define IR_REGSET_ARGS \
188+
(IR_REGSET(IR_REG_RDI) | IR_REGSET(IR_REG_RSI) | IR_REGSET(IR_REG_RDX) \
189+
| IR_REGSET(IR_REG_RCX) | IR_REGSET(IR_REG_R8) | IR_REGSET(IR_REG_R9) \
190+
| IR_REGSET_INTERVAL(IR_REG_XMM0, IR_REG_XMM7))
191+
180192
# if __has_attribute(preserve_none)
181193

182194
# define IR_HAVE_PRESERVE_NONE 1
@@ -197,6 +209,13 @@ enum _ir_reg {
197209
# define IR_REG_INT_PNARG12 IR_REG_RAX
198210

199211
# define IR_MAX_REG_ARGS 20 /* IR_REG_INT_PNARGS + IR_REG_FP_ARGS */
212+
213+
# define IR_REGSET_PNARGS \
214+
(IR_REGSET_INTERVAL(IR_REG_R12, IR_REG_R15) | IR_REGSET(IR_REG_RDI) \
215+
| IR_REGSET(IR_REG_RSI) | IR_REGSET(IR_REG_RDX) | IR_REGSET(IR_REG_RCX) \
216+
| IR_REGSET(IR_REG_R8) | IR_REGSET(IR_REG_R9) | IR_REGSET(IR_REG_R11) \
217+
| IR_REGSET(IR_REG_RAX) | IR_REGSET_INTERVAL(IR_REG_XMM0, IR_REG_XMM7))
218+
200219
# else /* !preserve_none */
201220
# define IR_MAX_REG_ARGS 14 /* IR_REG_INT_ARGS + IR_REG_FP_ARGS */
202221
# endif

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