fix: add delay after WDT reset for better stability

Author: peterdragun

esptool/targets/esp32c3.py

@@ -4,6 +4,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 import struct
+from time import sleep
 from typing import Dict
 
 from .esp32 import ESP32ROM
@@ -255,13 +256,14 @@ def _post_connect(self):
     def hard_reset(self):
         if self.uses_usb_jtag_serial():
             self.rtc_wdt_reset()
+            sleep(0.5)  # wait for reset to take effect
         else:
             ESPLoader.hard_reset(self)
 
     def rtc_wdt_reset(self):
         print("Hard resetting with RTC WDT...")
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
-        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000)  # set WDT timeout
+        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000)  # set WDT timeout
         self.write_reg(
             self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
         )  # enable WDT

esptool/targets/esp32p4.py

@@ -4,6 +4,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 import struct
+from time import sleep
 from typing import Dict
 
 from .esp32 import ESP32ROM
@@ -264,7 +265,7 @@ def check_spi_connection(self, spi_connection):
     def rtc_wdt_reset(self):
         print("Hard resetting with RTC WDT...")
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
-        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000)  # set WDT timeout
+        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000)  # set WDT timeout
         self.write_reg(
             self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
         )  # enable WDT
@@ -273,6 +274,7 @@ def rtc_wdt_reset(self):
     def hard_reset(self):
         if self.uses_usb_jtag_serial() or self.uses_usb_otg():
             self.rtc_wdt_reset()
+            sleep(0.5)  # wait for reset to take effect
         else:
             ESPLoader.hard_reset(self)
 

esptool/targets/esp32s2.py

@@ -4,6 +4,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 import struct
+from time import sleep
 from typing import Dict
 
 from .esp32 import ESP32ROM
@@ -290,7 +291,7 @@ def _post_connect(self):
     def rtc_wdt_reset(self):
         print("Hard resetting with RTC WDT...")
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
-        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000)  # set WDT timeout
+        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000)  # set WDT timeout
         self.write_reg(
             self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
         )  # enable WDT
@@ -307,6 +308,7 @@ def hard_reset(self):
                 and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
             ):
                 self.rtc_wdt_reset()
+                sleep(0.5)  # wait for reset to take effect
                 return
 
         ESPLoader.hard_reset(self, uses_usb_otg)

esptool/targets/esp32s3.py

@@ -4,6 +4,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 import struct
+from time import sleep
 from typing import Dict
 
 from .esp32 import ESP32ROM
@@ -354,7 +355,7 @@ def _post_connect(self):
     def rtc_wdt_reset(self):
         print("Hard resetting with RTC WDT...")
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
-        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000)  # set WDT timeout
+        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000)  # set WDT timeout
         self.write_reg(
             self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
         )  # enable WDT
@@ -380,6 +381,7 @@ def hard_reset(self):
                 and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
             ):
                 self.rtc_wdt_reset()
+                sleep(0.5)  # wait for reset to take effect
                 return
 
         ESPLoader.hard_reset(self, uses_usb_otg)