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feat(esp32h21): add ESP32H21 esptool support
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.gitlab-ci.yml

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@@ -118,6 +118,7 @@ host_tests_espefuse:
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- esp32s2
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- esp32s3
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- esp32s3beta2
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- esp32h21
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script:
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- coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip ${TARGET}
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# some .coverage files in sub-directories are not collected on some runners, move them first

espefuse/__init__.py

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import espefuse.efuse.esp32c6 as esp32c6_efuse
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import espefuse.efuse.esp32c61 as esp32c61_efuse
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import espefuse.efuse.esp32h2 as esp32h2_efuse
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import espefuse.efuse.esp32h21 as esp32h21_efuse
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import espefuse.efuse.esp32h2beta1 as esp32h2beta1_efuse
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import espefuse.efuse.esp32p4 as esp32p4_efuse
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import espefuse.efuse.esp32s2 as esp32s2_efuse
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"ESP32-C5(beta3)", esp32c5beta3_efuse, esptool.targets.ESP32C5BETA3ROM
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),
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"esp32h2": DefChip("ESP32-H2", esp32h2_efuse, esptool.targets.ESP32H2ROM),
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"esp32h21": DefChip("ESP32-H21", esp32h21_efuse, esptool.targets.ESP32H21ROM),
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"esp32p4": DefChip("ESP32-P4", esp32p4_efuse, esptool.targets.ESP32P4ROM),
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"esp32h2beta1": DefChip(
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"ESP32-H2(beta1)", esp32h2beta1_efuse, esptool.targets.ESP32H2BETA1ROM

espefuse/efuse/esp32h21/__init__.py

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from . import operations
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from .emulate_efuse_controller import EmulateEfuseController
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from .fields import EspEfuses
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# This file describes eFuses controller for ESP32-H21 chip
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#
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# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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import reedsolo
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from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters
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from ..emulate_efuse_controller_base import EmulateEfuseControllerBase, FatalError
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class EmulateEfuseController(EmulateEfuseControllerBase):
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"""The class for virtual efuse operation. Using for HOST_TEST."""
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CHIP_NAME = "ESP32-H21"
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mem = None
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debug = False
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def __init__(self, efuse_file=None, debug=False):
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self.Blocks = EfuseDefineBlocks
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self.Fields = EfuseDefineFields(None)
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self.REGS = EfuseDefineRegisters
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super(EmulateEfuseController, self).__init__(efuse_file, debug)
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self.write_reg(self.REGS.EFUSE_CMD_REG, 0)
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""" esptool method start >>"""
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def get_major_chip_version(self):
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return 0
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def get_minor_chip_version(self):
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return 0
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def get_crystal_freq(self):
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return 32 # MHz
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def get_security_info(self):
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return {
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"flags": 0,
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"flash_crypt_cnt": 0,
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"key_purposes": 0,
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"chip_id": 0,
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"api_version": 0,
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}
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""" << esptool method end """
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def handle_writing_event(self, addr, value):
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if addr == self.REGS.EFUSE_CMD_REG:
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if value & self.REGS.EFUSE_PGM_CMD:
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self.copy_blocks_wr_regs_to_rd_regs(updated_block=(value >> 2) & 0xF)
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self.clean_blocks_wr_regs()
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self.check_rd_protection_area()
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self.write_reg(addr, 0)
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self.write_reg(self.REGS.EFUSE_CMD_REG, 0)
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elif value == self.REGS.EFUSE_READ_CMD:
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self.write_reg(addr, 0)
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self.write_reg(self.REGS.EFUSE_CMD_REG, 0)
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self.save_to_file()
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def get_bitlen_of_block(self, blk, wr=False):
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if blk.id == 0:
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if wr:
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return 32 * 8
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else:
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return 32 * blk.len
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else:
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if wr:
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rs_coding = 32 * 3
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return 32 * 8 + rs_coding
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else:
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return 32 * blk.len
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def handle_coding_scheme(self, blk, data):
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if blk.id != 0:
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# CODING_SCHEME RS applied only for all blocks except BLK0.
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coded_bytes = 12
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data.pos = coded_bytes * 8
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plain_data = data.readlist("32*uint:8")[::-1]
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# takes 32 bytes
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# apply RS encoding
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rs = reedsolo.RSCodec(coded_bytes)
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# 32 byte of data + 12 bytes RS
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calc_encoded_data = list(rs.encode([x for x in plain_data]))
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data.pos = 0
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if calc_encoded_data != data.readlist("44*uint:8")[::-1]:
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raise FatalError("Error in coding scheme data")
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data = data[coded_bytes * 8 :]
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if blk.len < 8:
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data = data[(8 - blk.len) * 32 :]
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return data

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