@@ -64,7 +64,7 @@ pktgen_wire_size(port_info_t *pinfo)
6464 if (pktgen_tst_port_flags (pinfo , SEND_PCAP_PKTS )) {
6565 pcap_info_t * pcap = l2p_get_pcap (pinfo -> pid );
6666
67- size = WIRE_SIZE (pcap -> max_pkt_size , uint64_t );
67+ size = WIRE_SIZE (pcap -> avg_pkt_size , uint64_t );
6868 } else {
6969 if (unlikely (pinfo -> seqCnt > 0 )) {
7070 for (i = 0 ; i < pinfo -> seqCnt ; i ++ )
@@ -111,11 +111,10 @@ pktgen_packet_rate(port_info_t *port)
111111 pps = (((link_speed / pktgen_wire_size (port )) * (port -> tx_rate / txcnt )) / 100 );
112112 pps = ((pps > 0 ) ? pps : 1 );
113113
114- // cycles per burst is hz divided by pps times burst count
115- cpb = (rte_get_timer_hz () / pps ) * (uint64_t )port -> tx_burst ; /* Cycles per Burst */
116-
117- // divide up the work between the number of transmit queues, so multiple by queue count.
118- port -> tx_cycles = cpb * (uint64_t )txcnt ;
114+ // Do all multiplications first to reduce rounding errors.
115+ // Add pps/2 to do rounding instead of truncation.
116+ cpb = (pps / 2 + (uint64_t )txcnt * port -> tx_burst * rte_get_timer_hz ()) / pps ;
117+ port -> tx_cycles = cpb ;
119118 port -> tx_pps = pps ;
120119}
121120
@@ -1070,9 +1069,11 @@ pktgen_main_rxtx_loop(void)
10701069 curr_tsc = pktgen_get_time ();
10711070
10721071 /* Determine when is the next time to send packets */
1073- if (curr_tsc >= tx_next_cycle ) {
1074- tx_next_cycle = curr_tsc + pinfo -> tx_cycles ;
1075-
1072+ const int64_t max_tx_lag =
1073+ DEFAULT_MAX_TX_LAG ; // Allow some lag, ideally make this configurable.
1074+ int64_t dt = curr_tsc - tx_next_cycle ;
1075+ if (dt >= 0 ) {
1076+ tx_next_cycle = curr_tsc + pinfo -> tx_cycles - (dt <= max_tx_lag ? dt : 0 );
10761077 // Process TX
10771078 pktgen_main_transmit (pinfo , tx_qid );
10781079 }
@@ -1124,8 +1125,11 @@ pktgen_main_tx_loop(void)
11241125 curr_tsc = pktgen_get_time ();
11251126
11261127 /* Determine when is the next time to send packets */
1127- if (unlikely (curr_tsc >= tx_next_cycle )) {
1128- tx_next_cycle = curr_tsc + pinfo -> tx_cycles ;
1128+ const int64_t max_tx_lag =
1129+ DEFAULT_MAX_TX_LAG ; // Allow some lag, ideally make this configurable.
1130+ int64_t dt = curr_tsc - tx_next_cycle ;
1131+ if (dt >= 0 ) {
1132+ tx_next_cycle = curr_tsc + pinfo -> tx_cycles - (dt <= max_tx_lag ? dt : 0 );
11291133
11301134 // Process TX
11311135 pktgen_main_transmit (pinfo , tx_qid );
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