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Merge upstream changes
Resolve merge conflict in riscv_virtasm.ml by adopting upstream logic for La/Li instructions while preserving meaningful variable names.
2 parents a3f6430 + eda44e2 commit 57cf247

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src/riscv_reg.ml

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,12 +74,18 @@ module Reg = struct
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;;
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(* Reg寄存器最大可分配数量*)
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let k = 32
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let k = 11
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(* 用于调用者保存寄存器*)
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let caller_saved_regs =
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[ Ra; T0; T1; T2; A0; A1; A2; A3; A4; A5; A6; A7; T3; T4; T5; T6 ]
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;;
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let callee_saved_regs =
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[ S1; S2; S3; S4; S5; S6; S7; S8; S9; S10; S11 ]
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;;
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let spill_reg = T0
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;;
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end
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(* Module for floating-point registers (freg_t) *)

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