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Hamlin Li
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8355293: [TEST] RISC-V: enable more ir tests
Reviewed-by: fyang, luhenry
1 parent 3270a7d commit 862797f

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6 files changed

+36
-29
lines changed

6 files changed

+36
-29
lines changed

‎test/hotspot/jtreg/compiler/loopopts/superword/ProdRed_Double.java‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,10 @@ public static void prodReductionInit(double[] a, double[] b) {
8888
@IR(applyIfAnd = {"SuperWordReductions", "true", "LoopMaxUnroll", ">= 8"},
8989
applyIfCPUFeature = {"sse2", "true"},
9090
counts = {IRNode.MUL_REDUCTION_VD, ">= 1"})
91+
// There is no efficient way to implement strict-ordered version on riscv64.
92+
@IR(applyIf = {"SuperWordReductions", "true"},
93+
applyIfCPUFeature = {"rvv", "true"},
94+
failOn = {IRNode.MUL_REDUCTION_VD})
9195
public static double prodReductionImplement(double[] a, double[] b, double total) {
9296
for (int i = 0; i < a.length; i++) {
9397
total *= a[i] - b[i];
@@ -101,6 +105,10 @@ public static double prodReductionImplement(double[] a, double[] b, double total
101105
@IR(applyIfAnd = {"SuperWordReductions", "true", "LoopMaxUnroll", ">= 8"},
102106
applyIfCPUFeature = {"sse2", "true"},
103107
counts = {IRNode.MUL_REDUCTION_VD, ">= 1"})
108+
// There is no efficient way to implement strict-ordered version on riscv64.
109+
@IR(applyIf = {"SuperWordReductions", "true"},
110+
applyIfCPUFeature = {"rvv", "true"},
111+
failOn = {IRNode.MUL_REDUCTION_VD})
104112
public static double prodReductionWithStoreImplement(double[] a, double[] b, double[] c, double total) {
105113
for (int i = 0; i < a.length; i++) {
106114
c[i] = a[i] - b[i];

‎test/hotspot/jtreg/compiler/loopopts/superword/ProdRed_Float.java‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,10 @@ public static void prodReductionInit(float[] a, float[] b) {
8686
@IR(applyIfCPUFeature = {"sse4.1", "true"},
8787
applyIfAnd = {"SuperWordReductions", "true", "LoopMaxUnroll", ">= 8"},
8888
counts = {IRNode.MUL_REDUCTION_VF, ">= 1"})
89+
// There is no efficient way to implement strict-ordered version on riscv64.
90+
@IR(applyIfCPUFeature = {"rvv", "true"},
91+
applyIf = {"SuperWordReductions", "true"},
92+
failOn = {IRNode.MUL_REDUCTION_VF})
8993
public static float prodReductionImplement(float[] a, float[] b, float total) {
9094
for (int i = 0; i < a.length; i++) {
9195
total *= a[i] - b[i];

‎test/hotspot/jtreg/compiler/loopopts/superword/ProdRed_Int.java‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -85,8 +85,7 @@ public static void prodReductionInit(int[] a, int[] b) {
8585
@IR(applyIfCPUFeature = {"sse4.1", "true"},
8686
applyIfAnd = {"SuperWordReductions", "true", "LoopMaxUnroll", ">= 8"},
8787
counts = {IRNode.MUL_REDUCTION_VI, ">= 1", IRNode.MUL_REDUCTION_VI, "<= 2"}) // one for main-loop, one for vector-post-loop
88-
@IR(applyIfPlatform = {"riscv64", "true"},
89-
applyIfCPUFeature = {"rvv", "true"},
88+
@IR(applyIfCPUFeature = {"rvv", "true"},
9089
applyIfAnd = {"SuperWordReductions", "true", "LoopMaxUnroll", ">= 8"},
9190
counts = {IRNode.MUL_REDUCTION_VI, ">= 1", IRNode.MUL_REDUCTION_VI, "<= 2"}) // one for main-loop, one for vector-post-loop
9291
public static int prodReductionImplement(int[] a, int[] b, int total) {

‎test/hotspot/jtreg/compiler/rangechecks/TestRangeCheckHoistingScaledIV.java‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
/*
22
* Copyright (c) 2022, 2023, Arm Limited. All rights reserved.
3+
* Copyright (c) 2025, Rivos Inc. All rights reserved.
34
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
45
*
56
* This code is free software; you can redistribute it and/or modify it
@@ -27,7 +28,7 @@
2728
* @summary Test range check hoisting for some scaled iv at array index
2829
* @library /test/lib /
2930
* @requires vm.flagless
30-
* @requires vm.debug & vm.compiler2.enabled & (os.simpleArch == "x64" | os.arch == "aarch64")
31+
* @requires vm.debug & vm.compiler2.enabled & (os.simpleArch == "x64" | os.arch == "aarch64" | os.arch == "riscv64")
3132
* @modules jdk.incubator.vector
3233
* @run main/othervm compiler.rangechecks.TestRangeCheckHoistingScaledIV
3334
*/

‎test/hotspot/jtreg/compiler/vectorization/runner/ArrayShiftOpTest.java‎

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*
22
* Copyright (c) 2022, 2023, Arm Limited. All rights reserved.
33
* Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved.
4+
* Copyright (c) 2025, Rivos Inc. All rights reserved.
45
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
56
*
67
* This code is free software; you can redistribute it and/or modify it
@@ -75,12 +76,9 @@ public ArrayShiftOpTest() {
7576
}
7677

7778
@Test
78-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"},
79+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true", "rvv", "true"},
7980
counts = {IRNode.STORE_VECTOR, ">0"})
80-
@IR(applyIfCPUFeature = {"avx512f", "true"},
81-
counts = {IRNode.ROTATE_RIGHT_V, ">0"})
82-
@IR(applyIfPlatform = {"riscv64", "true"},
83-
applyIfCPUFeature = {"zvbb", "true"},
81+
@IR(applyIfCPUFeatureOr = {"avx512f", "true", "zvbb", "true"},
8482
counts = {IRNode.ROTATE_RIGHT_V, ">0"})
8583
public int[] intCombinedRotateShift() {
8684
int[] res = new int[SIZE];
@@ -91,9 +89,9 @@ public int[] intCombinedRotateShift() {
9189
}
9290

9391
@Test
94-
@IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"},
92+
@IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true", "rvv", "true"},
9593
counts = {IRNode.STORE_VECTOR, ">0"})
96-
@IR(applyIfCPUFeature = {"avx512f", "true"},
94+
@IR(applyIfCPUFeatureOr = {"avx512f", "true", "zvbb", "true"},
9795
counts = {IRNode.ROTATE_RIGHT_V, ">0"})
9896
// Requires size to not be known at compile time, otherwise the shift
9997
// can get constant folded with the (iv + const) pattern from the
@@ -107,12 +105,9 @@ public int[] intCombinedRotateShiftWithPopulateIndex() {
107105
}
108106

109107
@Test
110-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"},
108+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true", "rvv", "true"},
111109
counts = {IRNode.STORE_VECTOR, ">0"})
112-
@IR(applyIfCPUFeature = {"avx512f", "true"},
113-
counts = {IRNode.ROTATE_RIGHT_V, ">0"})
114-
@IR(applyIfPlatform = {"riscv64", "true"},
115-
applyIfCPUFeature = {"zvbb", "true"},
110+
@IR(applyIfCPUFeatureOr = {"avx512f", "true", "zvbb", "true"},
116111
counts = {IRNode.ROTATE_RIGHT_V, ">0"})
117112
public long[] longCombinedRotateShift() {
118113
long[] res = new long[SIZE];
@@ -135,9 +130,9 @@ public long[] longExplicitRotateWithPopulateIndex() {
135130
}
136131

137132
@Test
138-
@IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"},
133+
@IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true", "rvv", "true"},
139134
counts = {IRNode.STORE_VECTOR, ">0"})
140-
@IR(applyIfCPUFeature = {"avx512f", "true"},
135+
@IR(applyIfCPUFeatureOr = {"avx512f", "true", "zvbb", "true"},
141136
counts = {IRNode.ROTATE_RIGHT_V, ">0"})
142137
@IR(applyIfCPUFeatureOr = {"sve", "true", "avx2", "true"},
143138
counts = {IRNode.POPULATE_INDEX, ">0"})

‎test/hotspot/jtreg/compiler/vectorization/runner/BasicIntOpTest.java‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ public BasicIntOpTest() {
6464

6565
// ---------------- Arithmetic ----------------
6666
@Test
67-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
67+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
6868
counts = {IRNode.SUB_VI, ">0"})
6969
public int[] vectorNeg() {
7070
int[] res = new int[SIZE];
@@ -75,7 +75,7 @@ public int[] vectorNeg() {
7575
}
7676

7777
@Test
78-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "ssse3", "true"},
78+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "ssse3", "true", "rvv", "true"},
7979
counts = {IRNode.ABS_VI, ">0"})
8080
public int[] vectorAbs() {
8181
int[] res = new int[SIZE];
@@ -86,7 +86,7 @@ public int[] vectorAbs() {
8686
}
8787

8888
@Test
89-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
89+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
9090
counts = {IRNode.ADD_VI, ">0"})
9191
public int[] vectorAdd() {
9292
int[] res = new int[SIZE];
@@ -97,7 +97,7 @@ public int[] vectorAdd() {
9797
}
9898

9999
@Test
100-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
100+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
101101
counts = {IRNode.SUB_VI, ">0"})
102102
public int[] vectorSub() {
103103
int[] res = new int[SIZE];
@@ -108,7 +108,7 @@ public int[] vectorSub() {
108108
}
109109

110110
@Test
111-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"},
111+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true", "rvv", "true"},
112112
counts = {IRNode.MUL_VI, ">0"})
113113
public int[] vectorMul() {
114114
int[] res = new int[SIZE];
@@ -119,7 +119,7 @@ public int[] vectorMul() {
119119
}
120120

121121
@Test
122-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"},
122+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true", "rvv", "true"},
123123
counts = {IRNode.MUL_VI, ">0", IRNode.ADD_VI, ">0"})
124124
public int[] vectorMulAdd() {
125125
int[] res = new int[SIZE];
@@ -130,7 +130,7 @@ public int[] vectorMulAdd() {
130130
}
131131

132132
@Test
133-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true"},
133+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse4.1", "true", "rvv", "true"},
134134
counts = {IRNode.MUL_VI, ">0", IRNode.SUB_VI, ">0"})
135135
public int[] vectorMulSub() {
136136
int[] res = new int[SIZE];
@@ -141,7 +141,7 @@ public int[] vectorMulSub() {
141141
}
142142

143143
@Test
144-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"},
144+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true", "rvv", "true"},
145145
counts = {IRNode.POPCOUNT_VI, ">0"})
146146
public int[] vectorPopCount() {
147147
int[] res = new int[SIZE];
@@ -153,7 +153,7 @@ public int[] vectorPopCount() {
153153

154154
// ---------------- Logic ----------------
155155
@Test
156-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
156+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
157157
counts = {IRNode.XOR_VI, ">0"})
158158
public int[] vectorNot() {
159159
int[] res = new int[SIZE];
@@ -164,7 +164,7 @@ public int[] vectorNot() {
164164
}
165165

166166
@Test
167-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
167+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
168168
counts = {IRNode.AND_VI, ">0"})
169169
public int[] vectorAnd() {
170170
int[] res = new int[SIZE];
@@ -175,7 +175,7 @@ public int[] vectorAnd() {
175175
}
176176

177177
@Test
178-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
178+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
179179
counts = {IRNode.OR_VI, ">0"})
180180
public int[] vectorOr() {
181181
int[] res = new int[SIZE];
@@ -186,7 +186,7 @@ public int[] vectorOr() {
186186
}
187187

188188
@Test
189-
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
189+
@IR(applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true", "rvv", "true"},
190190
counts = {IRNode.XOR_VI, ">0"})
191191
public int[] vectorXor() {
192192
int[] res = new int[SIZE];

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