notes

Author: Autoparallel

src/compiler/mod.rs

@@ -16,6 +16,11 @@ use petgraph::graph::{DiGraph, NodeIndex};
 // }
 // ```
 // So we can do things like `impl Add`, `impl Mul` for variables and make them into gates?
+
+// Above seems done. Now we need to have a way to unravel a collection of expressions into a
+// circuit that may have the same inputs and outputs as the expressions. Inputs are going to be
+// the terminal variables found by fully unravelling expressions and they should be named. The
+// fully ravelled expressions are the outputs, and they can also be named
 use super::*;
 
 pub mod dsl;
@@ -58,4 +63,3 @@ pub struct Circuit {
 impl Circuit {
   pub fn new() -> Self { Self { gates: DiGraph::new() } }
 }
-