DDR read and write test in core 3 -U54_3

[nileena-dev]

i want to implement an application that verifies ethernet and ddr read/write operations. My custom board has GEM1 for ethernet (local interrupt is in core 3), i want ddr_test program also in the same core. I am using ddr_read_write function provided by polarfire for the same. is there anything i should be worried about, since after loading the program i am getting some read failures in non-cached and code get stuck at cached read?

/-------------------------MACRO DEFINITIONS----------------------------------/
#define small_ver 0x00010000UL
#define DDR_BASE 0x80000000u
#define DDR_SIZE 0x40000000u
#define MIN_OFFSET 1U
#define MAX_OFFSET 16U
#define TIMER_INCREMENT 1

/----------------------------------------------------------------------------/
uint8_t data_block[256];
uint64_t hart_jump_ddr = 0U;
volatile uint32_t g_10ms_count;
mss_uart_instance_t *g_debug_uart= &g_mss_uart0_lo ;

/----------------------------------------------------------------------------/
void DDR_Task( void )
{
ddr_test(small_ver);
}

/----------------------------------------------------------------------------/
static void ddr_test (uint32_t num_access)
{
uint64_t mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +
(LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U);
uint32_t max_num_access = mem_size/8U;
if (num_access > max_num_access)
{
num_access = max_num_access;
}
if(start_address >= 0x80000000UL && start_address <= 0xBFFFFFFFUL)
{
sprintf(info_string,"Executing from DDR \r\n");
MSS_UART_polled_tx(&g_mss_uart0_lo, info_string,strlen(info_string));
}
else
{
ASSERT(0);
}
setup_ddr_segments(DEFAULT_SEG_SETUP);
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\r Accessing DDR Non Cached ");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
ddr_read_write_fn((uint64_t*)(LIBERO_SETTING_DDR_64_NON_CACHE + (1024 * 128)),(uint32_t)num_access,SW_CONFIG_PATTERN);
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\r Finished ");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\r Accessing DDR Cached ");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
ddr_read_write_fn((uint64_t*)(LIBERO_SETTING_DDR_64_CACHE + (1024 * 128)),(uint32_t)(num_access * 32),SW_CONFIG_PATTERN);
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\r Finished ");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
setup_ddr_segments(LIBERO_SEG_SETUP);
}

Also

#ifndef MPFS_HAL_FIRST_HART
#define MPFS_HAL_FIRST_HART 3
#endif

#ifndef MPFS_HAL_LAST_HART
#define MPFS_HAL_LAST_HART 3
#endif

#define SGMII_SUPPORT
#define DDR_SUPPORT
#define MSSIO_SUPPORT

#define DEBUG_DDR_INIT
#define DEBUG_DDR_RD_RW_FAIL
//#define DEBUG_DDR_RD_RW_PASS
//#define DEBUG_DDR_CFG_DDR_SGMII_PHY
//#define DEBUG_DDR_DDRCFG