DDR Training of polarfire soc discovery kit reference design #521
Replies: 2 comments
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I have seen this a number of times, but not consistently, on my MPFS-DISCO-KIT using the 2025.03 release of the reference design. In my case it seems to happen only when the board has been on for a little while, so I was assuming that its caused by a thermal issue with the DDR controller, but I have not done anything to test that conclusion. |
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We have seen this as well since months ago and we found it might help if you brute-force the cycling over all the allowed values for the reference clock offsets (CK/CA additive offset) , 0 - 7 per the datasheet, to find a stable timing window for the DDR interface.. As a hint you can try this in You might also want to do a small research of what these values means, and to arrange/sort these values in some more meaningful fashion that will help the DDR training pass even faster. Here is also a link that might be related to the issue, we've found it as a possible justification to our solely empirical findings thru debugging: Would be nice if you post back your results if these hints were helpfull with some benchmarks Cheers, |
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Hello,
[What I did]
I programed following job file to the PolarFire Discovery Kit.
2024.06 latest
MPFS_DISCOVERY.zip
https://github.com/polarfire-soc/polarfire-soc-discovery-kit-reference-design/releases/tag/v2024.06
[Result]
In Terminal, DDR Training was stopped at 80%
DDR training ...
80% [ ..........]
[Request]
If the file is wrong, I would like to ask Microchip to correct the file.
[For reference]
Others also stop DDR training at 80%.
https://forum.beagleboard.org/t/anyone-tried-the-discovery-kit-from-microchip/38144/45
Thank you for reading.
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