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| 1 | +#include "common/passert.h" |
| 2 | + |
| 3 | +namespace pound::jit::decoder { |
| 4 | +typedef enum |
| 5 | +{ |
| 6 | + IR_TYPE_VOID = 0, |
| 7 | + IR_TYPE_U1 = 1 << 0, |
| 8 | + IR_TYPE_U8 = 1 << 1, |
| 9 | + IR_TYPE_U16 = 1 << 2, |
| 10 | + IR_TYPE_U32 = 1 << 3, |
| 11 | + IR_TYPE_U64 = 1 << 4, |
| 12 | + IR_TYPE_U128 = 1 << 5, |
| 13 | + IR_TYPE_A32_REG = 1 << 6, // ARM32 GPR R0-R14 |
| 14 | + IR_TYPE_A32_EXT_REG = 1 << 7, // ARM32 Extended Registers (e.g., for |
| 15 | + // VFP/NEON, or just R15 if treated specially) |
| 16 | + IR_TYPE_A32_CPSR = 1 << 8, // ARM32 CPSR/SPSR |
| 17 | + IR_TYPE_COND = 1 << 9, // Condition codes |
| 18 | + IR_TYPE_ACC_TYPE = 1 << 10, // Memory access type |
| 19 | + IR_TYPE_OPAQUE |
| 20 | + = 1 << 11, // Represents a value defined by another IR instruction |
| 21 | +} ir_type_t; |
| 22 | + |
| 23 | +void |
| 24 | +ir_type_name (const ir_type_t type, char *p_out_name, size_t size, size_t capacity) |
| 25 | +{ |
| 26 | + PVM_ASSERT(nullptr != p_out_name); |
| 27 | + |
| 28 | + const char **names = { "A32Reg", "A32ExtReg", "Opaque", "U1", "U8", |
| 29 | + "U16", "U32", "U64", "U128", "Cond" }; |
| 30 | + size_t names_size = 10; |
| 31 | + const size_t bits = (size_t)type; |
| 32 | + if (0 == bits) |
| 33 | + { |
| 34 | + *p_out_name = "Void"; |
| 35 | + } |
| 36 | + else |
| 37 | + { |
| 38 | + for (size_t i = 0; i < names_size; ++i) |
| 39 | + { |
| 40 | + if (0 != (bits & (size_t(1) << i))) |
| 41 | + { |
| 42 | + if('\0' != *p_out_name) |
| 43 | + { |
| 44 | + //Append | to name. |
| 45 | + } |
| 46 | + } |
| 47 | + } |
| 48 | + } |
| 49 | +} |
| 50 | + |
| 51 | +bool |
| 52 | +ir_are_types_compatible (const ir_type_t t1, const ir_type_t t2) |
| 53 | +{ |
| 54 | + const bool is_compatible |
| 55 | + = (t1 == t2) || (IR_TYPE_OPAQUE == t1) || (IR_TYPE_OPAQUE == t2); |
| 56 | + return is_compatible; |
| 57 | +} |
| 58 | +} |
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