From 7e37b3ced3f2abbf88dc52db86e5216bd4c0fa31 Mon Sep 17 00:00:00 2001 From: Anders Date: Fri, 6 Sep 2024 18:34:15 -0700 Subject: [PATCH] handle simple assignments patterns on left-hand-side (lhs) logic [31:0]data[4], a, b, c, d; assign '{ a, b, c, d } = data; --- src/slang_frontend.cc | 13 +++++++++++++ tests/various/simple_assignment_pattern_lhs.sv | 12 ++++++++++++ tests/various/simple_assignment_pattern_lhs.ys | 1 + 3 files changed, 26 insertions(+) create mode 100644 tests/various/simple_assignment_pattern_lhs.sv create mode 100644 tests/various/simple_assignment_pattern_lhs.ys diff --git a/src/slang_frontend.cc b/src/slang_frontend.cc index 3fe6454..c1c5d82 100644 --- a/src/slang_frontend.cc +++ b/src/slang_frontend.cc @@ -1349,6 +1349,19 @@ RTLIL::SigSpec SignalEvalContext::lhs(const ast::Expression &expr) expr.type->getBitstreamWidth()); } break; + case ast::ExpressionKind::SimpleAssignmentPattern: + { + const ast::SimpleAssignmentPatternExpression &pattern_expr = expr.as(); + for (auto op : pattern_expr.elements()) + ret = {ret, lhs(*op)}; + } + break; + case ast::ExpressionKind::Assignment: + { + const ast::AssignmentExpression &ae = expr.as(); + ret = lhs(ae.left()); + } + break; default: unimplemented(expr); break; diff --git a/tests/various/simple_assignment_pattern_lhs.sv b/tests/various/simple_assignment_pattern_lhs.sv new file mode 100644 index 0000000..f248508 --- /dev/null +++ b/tests/various/simple_assignment_pattern_lhs.sv @@ -0,0 +1,12 @@ +module top(); + +logic [31:0]data[4] = '{ 4 { 32'hdeadbeef } }; + +logic [31:0]a, b, c, d; + +// should allow mismatched size +//assign '{ {a[15:0], b[31:16]}, { b[15:0], a[31:24] }, c, d } = data; + +assign '{ {a[15:0], b[31:16]}, { b[15:0], a[31:16] }, c, d } = data; + +endmodule diff --git a/tests/various/simple_assignment_pattern_lhs.ys b/tests/various/simple_assignment_pattern_lhs.ys new file mode 100644 index 0000000..c8e568f --- /dev/null +++ b/tests/various/simple_assignment_pattern_lhs.ys @@ -0,0 +1 @@ +read_slang simple_assignment_pattern_lhs.sv