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39 | 39 | # MREDUCE_4X(_v0, _v1, _v2, _v3) |
40 | 40 | # |
41 | 41 | .macro MREDUCE_4X _v0 _v1 _v2 _v3 |
42 | | - lxvd2x 32+13, 0, 3 |
43 | | - addi 3, 3, 16 |
44 | | - lxvd2x 32+18, 0, 3 |
45 | | - addi 3, 3, 16 |
46 | | - lxvd2x 32+23, 0, 3 |
47 | | - addi 3, 3, 16 |
48 | | - lxvd2x 32+7, 0, 3 |
49 | | - addi 3, 3, 16 |
50 | | - |
51 | | - vmladduhm 15, 13, V1353, 3 |
52 | | - vmladduhm 20, 18, V1353, 3 |
53 | | - vmladduhm 25, 23, V1353, 3 |
54 | | - vmladduhm 9, 7, V1353, 3 |
55 | | - |
56 | | - vmhraddshs 14, 13, V1353, 3 |
57 | | - vmhraddshs 19, 18, V1353, 3 |
58 | | - vmhraddshs 24, 23, V1353, 3 |
59 | | - vmhraddshs 8, 7, V1353, 3 |
60 | | - |
61 | | - vmladduhm 15, 15, V_QINV, 3 |
62 | | - vmladduhm 20, 20, V_QINV, 3 |
63 | | - vmladduhm 25, 25, V_QINV, 3 |
64 | | - vmladduhm 9, 9, V_QINV, 3 |
65 | | - |
66 | | - vmhraddshs 15, 15, V_NMKQ, 14 |
67 | | - vmhraddshs 20, 20, V_NMKQ, 19 |
68 | | - vmhraddshs 25, 25, V_NMKQ, 24 |
69 | | - vmhraddshs 9, 9, V_NMKQ, 8 |
70 | | - |
71 | | - vsrah \_v0, 15, 4 # >> 1 |
72 | | - vsrah \_v1, 20, 4 # >> 1 |
73 | | - vsrah \_v2, 25, 4 # >> 1 |
74 | | - vsrah \_v3, 9, 4 # >> 1 |
| 42 | + lxvd2x 32+13, 0, 3 |
| 43 | + addi 3, 3, 16 |
| 44 | + lxvd2x 32+18, 0, 3 |
| 45 | + addi 3, 3, 16 |
| 46 | + lxvd2x 32+23, 0, 3 |
| 47 | + addi 3, 3, 16 |
| 48 | + lxvd2x 32+7, 0, 3 |
| 49 | + addi 3, 3, 16 |
| 50 | + |
| 51 | + vmladduhm 15, 13, V1353, 3 |
| 52 | + vmladduhm 20, 18, V1353, 3 |
| 53 | + vmladduhm 25, 23, V1353, 3 |
| 54 | + vmladduhm 9, 7, V1353, 3 |
| 55 | + |
| 56 | + vmhraddshs 14, 13, V1353, 3 |
| 57 | + vmhraddshs 19, 18, V1353, 3 |
| 58 | + vmhraddshs 24, 23, V1353, 3 |
| 59 | + vmhraddshs 8, 7, V1353, 3 |
| 60 | + |
| 61 | + vmladduhm 15, 15, V_QINV, 3 |
| 62 | + vmladduhm 20, 20, V_QINV, 3 |
| 63 | + vmladduhm 25, 25, V_QINV, 3 |
| 64 | + vmladduhm 9, 9, V_QINV, 3 |
| 65 | + |
| 66 | + vmhraddshs 15, 15, V_NMKQ, 14 |
| 67 | + vmhraddshs 20, 20, V_NMKQ, 19 |
| 68 | + vmhraddshs 25, 25, V_NMKQ, 24 |
| 69 | + vmhraddshs 9, 9, V_NMKQ, 8 |
| 70 | + |
| 71 | + vsrah \_v0, 15, 4 # >> 1 |
| 72 | + vsrah \_v1, 20, 4 # >> 1 |
| 73 | + vsrah \_v2, 25, 4 # >> 1 |
| 74 | + vsrah \_v3, 9, 4 # >> 1 |
75 | 75 | .endm |
76 | 76 |
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77 | 77 | .macro Write_8X |
78 | | - stxvd2x 32+27, 4, 3 |
79 | | - stxvd2x 32+28, 5, 3 |
80 | | - stxvd2x 32+29, 6, 3 |
81 | | - stxvd2x 32+30, 7, 3 |
82 | | - stxvd2x 32+13, 8, 3 |
83 | | - stxvd2x 32+18, 9, 3 |
84 | | - stxvd2x 32+23, 10, 3 |
85 | | - stxvd2x 32+7, 11, 3 |
| 78 | + stxvd2x 32+27, 4, 3 |
| 79 | + stxvd2x 32+28, 5, 3 |
| 80 | + stxvd2x 32+29, 6, 3 |
| 81 | + stxvd2x 32+30, 7, 3 |
| 82 | + stxvd2x 32+13, 8, 3 |
| 83 | + stxvd2x 32+18, 9, 3 |
| 84 | + stxvd2x 32+23, 10, 3 |
| 85 | + stxvd2x 32+7, 11, 3 |
86 | 86 | .endm |
87 | 87 |
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88 | 88 | .align 4 |
89 | 89 | .globl MLK_ASM_NAMESPACE(poly_tomont_ppc) |
90 | 90 | MLK_ASM_FN_SYMBOL(poly_tomont_ppc) |
91 | | - stdu 1, -320(1) |
92 | | - mflr 0 |
93 | | - |
94 | | - li 6, 128 |
95 | | - li 7, 144 |
96 | | - li 8, 160 |
97 | | - li 9, 176 |
98 | | - li 10, 192 |
99 | | - li 11, 208 |
100 | | - li 12, 224 |
101 | | - stxvx 32+20, 6, 1 |
102 | | - stxvx 32+21, 7, 1 |
103 | | - stxvx 32+22, 8, 1 |
104 | | - stxvx 32+23, 9, 1 |
105 | | - stxvx 32+24, 10, 1 |
106 | | - stxvx 32+25, 11, 1 |
107 | | - stxvx 32+26, 12, 1 |
108 | | - li 6, 240 |
109 | | - li 7, 256 |
110 | | - li 8, 272 |
111 | | - li 9, 288 |
112 | | - stxvx 32+27, 6, 1 |
113 | | - stxvx 32+28, 7, 1 |
114 | | - stxvx 32+29, 8, 1 |
115 | | - stxvx 32+30, 9, 1 |
116 | | - |
117 | | - li 6, NQ_OFFSET |
118 | | - li 7, QINV_OFFSET |
119 | | - li 8, C1353_OFFSET |
120 | | - lxvx 32+V_NMKQ, 6, 4 |
121 | | - lxvx 32+V_QINV, 7, 4 |
122 | | - lxvx 32+V1353, 8, 4 |
123 | | - |
124 | | - vxor 3, 3, 3 |
125 | | - vspltish 4, 1 |
126 | | - |
127 | | - li 4, -128 |
128 | | - li 5, -112 |
129 | | - li 6, -96 |
130 | | - li 7, -80 |
131 | | - li 8, -64 |
132 | | - li 9, -48 |
133 | | - li 10, -32 |
134 | | - li 11, -16 |
135 | | - |
136 | | - MREDUCE_4X 27, 28, 29, 30 |
137 | | - MREDUCE_4X 13, 18, 23, 7 |
138 | | - Write_8X |
139 | | - |
140 | | - MREDUCE_4X 27, 28, 29, 30 |
141 | | - MREDUCE_4X 13, 18, 23, 7 |
142 | | - Write_8X |
143 | | - |
144 | | - MREDUCE_4X 27, 28, 29, 30 |
145 | | - MREDUCE_4X 13, 18, 23, 7 |
146 | | - Write_8X |
147 | | - |
148 | | - MREDUCE_4X 27, 28, 29, 30 |
149 | | - MREDUCE_4X 13, 18, 23, 7 |
150 | | - Write_8X |
151 | | - |
152 | | - li 6, 128 |
153 | | - li 7, 144 |
154 | | - li 8, 160 |
155 | | - li 9, 176 |
156 | | - li 10, 192 |
157 | | - li 11, 208 |
158 | | - li 12, 224 |
159 | | - lxvx 32+20, 6, 1 |
160 | | - lxvx 32+21, 7, 1 |
161 | | - lxvx 32+22, 8, 1 |
162 | | - lxvx 32+23, 9, 1 |
163 | | - lxvx 32+24, 10, 1 |
164 | | - lxvx 32+25, 11, 1 |
165 | | - lxvx 32+26, 12, 1 |
166 | | - li 6, 240 |
167 | | - li 7, 256 |
168 | | - li 8, 272 |
169 | | - li 9, 288 |
170 | | - lxvx 32+27, 6, 1 |
171 | | - lxvx 32+28, 7, 1 |
172 | | - lxvx 32+29, 8, 1 |
173 | | - lxvx 32+30, 9, 1 |
174 | | - mtlr 0 |
175 | | - addi 1, 1, 320 |
176 | | - blr |
| 91 | + stdu 1, -320(1) |
| 92 | + mflr 0 |
| 93 | + |
| 94 | + li 6, 128 |
| 95 | + li 7, 144 |
| 96 | + li 8, 160 |
| 97 | + li 9, 176 |
| 98 | + li 10, 192 |
| 99 | + li 11, 208 |
| 100 | + li 12, 224 |
| 101 | + stxvx 32+20, 6, 1 |
| 102 | + stxvx 32+21, 7, 1 |
| 103 | + stxvx 32+22, 8, 1 |
| 104 | + stxvx 32+23, 9, 1 |
| 105 | + stxvx 32+24, 10, 1 |
| 106 | + stxvx 32+25, 11, 1 |
| 107 | + stxvx 32+26, 12, 1 |
| 108 | + li 6, 240 |
| 109 | + li 7, 256 |
| 110 | + li 8, 272 |
| 111 | + li 9, 288 |
| 112 | + stxvx 32+27, 6, 1 |
| 113 | + stxvx 32+28, 7, 1 |
| 114 | + stxvx 32+29, 8, 1 |
| 115 | + stxvx 32+30, 9, 1 |
| 116 | + |
| 117 | + li 6, NQ_OFFSET |
| 118 | + li 7, QINV_OFFSET |
| 119 | + li 8, C1353_OFFSET |
| 120 | + lxvx 32+V_NMKQ, 6, 4 |
| 121 | + lxvx 32+V_QINV, 7, 4 |
| 122 | + lxvx 32+V1353, 8, 4 |
| 123 | + |
| 124 | + vxor 3, 3, 3 |
| 125 | + vspltish 4, 1 |
| 126 | + |
| 127 | + li 4, -128 |
| 128 | + li 5, -112 |
| 129 | + li 6, -96 |
| 130 | + li 7, -80 |
| 131 | + li 8, -64 |
| 132 | + li 9, -48 |
| 133 | + li 10, -32 |
| 134 | + li 11, -16 |
| 135 | + |
| 136 | + MREDUCE_4X 27, 28, 29, 30 |
| 137 | + MREDUCE_4X 13, 18, 23, 7 |
| 138 | + Write_8X |
| 139 | + |
| 140 | + MREDUCE_4X 27, 28, 29, 30 |
| 141 | + MREDUCE_4X 13, 18, 23, 7 |
| 142 | + Write_8X |
| 143 | + |
| 144 | + MREDUCE_4X 27, 28, 29, 30 |
| 145 | + MREDUCE_4X 13, 18, 23, 7 |
| 146 | + Write_8X |
| 147 | + |
| 148 | + MREDUCE_4X 27, 28, 29, 30 |
| 149 | + MREDUCE_4X 13, 18, 23, 7 |
| 150 | + Write_8X |
| 151 | + |
| 152 | + li 6, 128 |
| 153 | + li 7, 144 |
| 154 | + li 8, 160 |
| 155 | + li 9, 176 |
| 156 | + li 10, 192 |
| 157 | + li 11, 208 |
| 158 | + li 12, 224 |
| 159 | + lxvx 32+20, 6, 1 |
| 160 | + lxvx 32+21, 7, 1 |
| 161 | + lxvx 32+22, 8, 1 |
| 162 | + lxvx 32+23, 9, 1 |
| 163 | + lxvx 32+24, 10, 1 |
| 164 | + lxvx 32+25, 11, 1 |
| 165 | + lxvx 32+26, 12, 1 |
| 166 | + li 6, 240 |
| 167 | + li 7, 256 |
| 168 | + li 8, 272 |
| 169 | + li 9, 288 |
| 170 | + lxvx 32+27, 6, 1 |
| 171 | + lxvx 32+28, 7, 1 |
| 172 | + lxvx 32+29, 8, 1 |
| 173 | + lxvx 32+30, 9, 1 |
| 174 | + mtlr 0 |
| 175 | + addi 1, 1, 320 |
| 176 | + blr |
177 | 177 |
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178 | 178 | /* To facilitate single-compilation-unit (SCU) builds, undefine all macros. |
179 | 179 | * Don't modify by hand -- this is auto-generated by scripts/autogen. */ |
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