docs: use the new admonitions feature.

Author: wanda-phi

docs/src/spartan3/clb.md

@@ -1,6 +1,7 @@
 # Logic block
 
-<div class="warning">This document describes Spartan 3 and Virtex 4 CLBs, since they are very similar.</div>
+> [!NOTE]
+> This document describes Spartan 3 and Virtex 4 CLBs, since they are very similar.
 
 The main logic resource in Spartan 3 and Virtex 4 devices is the CLB (Configurable Logic Block). It is based on the [Virtex 2 CLB](../virtex2/clb.md), but has significant changes, particularly to the LUT RAM structures.
 
@@ -262,7 +263,8 @@ The `FXINA` and `FXINB` inputs are routed as follows:
 | `SLICE2` | `SLICE0.FX` | `SLICE1.FX`                 | `MUXF7`             |
 | `SLICE3` | `SLICE2.FX` | `SLICE2.FX`, from CLB above | `MUXF8`             |
 
-<div class="warning">The routing is different from Virtex 2.</div>
+> [!NOTE]
+> The routing is different from Virtex 2.
 
 The `FX` output isn't connected across any interconnect holes — a `MUXF8` cannot be made of two CLBs separated by a hole.
 

docs/src/spartan3/interconnect/README.md

@@ -37,7 +37,8 @@ The core of the interconnect is made of the following wires, each of which is in
   | `OMUX14` | `W`, then `N` | `OMUX14.W`      | `OMUX12.WN`     |
   | `OMUX15` | `N`           | `OMUX15.N`      |
 
-  <div class="warning">this table is very similar to, but subtly different from the corresponding Virtex 2 table (the differences are in `OMUX9` and `OMUX13`).</div>
+  > [!NOTE]
+  > This table is very similar to, but subtly different from the corresponding Virtex 2 table (the differences are in `OMUX9` and `OMUX13`).
 
 - Double lines going in the cardinal directions, 8 per direction, called `DBL.[EWSN][0-7]`. Each of them has three segments, called `DBL.[EWSN][0-7].[0-2]`, where `.0` is located in the source tile and is driven, `.1` is in the next tile in the relevant direction, and `.2` is in the next tile after that. Some of the lines additionally have a fourth segment:
 

docs/src/xc9500/jtag.md

@@ -186,11 +186,12 @@ from the database.  When successful, the low two bits of
 DR will become `0b11`.  Note that shifting DR again before the operation is complete will
 abort it and return `0b00` in the low bits.
 
-<div class="warning">The timeout value of 1.3s present in the database is taken directly from ISE SVFs,
+> [!CAUTION]
+> The timeout value of 1.3s present in the database is taken directly from ISE SVFs,
 but it appears to be too small for the two devices I (@wanda-phi) personally possess,
 which require a timeout of 2s.  Since these devices came from random ebay listings, this
 may be due to age or mishandling.  Still, you may want to consider using a larger timeout
-in your programming software.</div>
+in your programming software.
 
 To erase fuses:
 

docs/src/xpla3/jtag.md

@@ -54,7 +54,8 @@ The boundary scan register contains the following bits, in order from **MSB**:
 
 All bits of the register are `BC_1` type cells.
 
-<div class="warning">The GCLK cells can reliably capture pin state in EXTEST mode, but only partially override internal connections in INTEST mode: connections through ZIA are overriden by the boundary register value, but connections through per-FB `FCLK` lines are not.</div>
+> [!IMPORTANT]
+> The GCLK cells can reliably capture pin state in EXTEST mode, but only partially override internal connections in INTEST mode: connections through ZIA are overriden by the boundary register value, but connections through per-FB `FCLK` lines are not.
 
 TODO: details on the cell connection, EXTEST, INTEST semantics