--wip-- [skip ci]

Author: ithinuel

Cargo.lock

@@ -5,6 +5,7 @@ use jep106::JEP106Code;
 use probe_rs::{
     architecture::{
         arm::{
+            ap::ApClass,
             armv6m::Demcr,
             component::Scs,
             dp::{DebugPortId, DebugPortVersion, MinDpSupport, DLPIDR, DPIDR, TARGETID},
@@ -13,8 +14,7 @@ use probe_rs::{
                 Component, ComponentId, CoresightComponent, PeripheralType,
             },
             sequences::DefaultArmSequence,
-            ApInformation, ArmProbeInterface, DpAddress, FullyQualifiedApAddress,
-            MemoryApInformation, Register,
+            ArmProbeInterface, DpAddress, FullyQualifiedApAddress, Register,
         },
         riscv::communication_interface::RiscvCommunicationInterface,
         xtensa::communication_interface::{
@@ -296,49 +296,37 @@ fn show_arm_info(interface: &mut dyn ArmProbeInterface, dp: DpAddress) -> Result
     if access_ports.is_empty() {
         println!("No access ports found on this chip.");
     } else {
-        for ap in access_ports {
-            let ap_information = interface.ap_information(&ap)?;
-
-            match ap_information {
-                ApInformation::MemoryAp(MemoryApInformation {
-                    debug_base_address,
-                    address,
-                    device_enabled,
-                    ..
-                }) => {
-                    let mut ap_nodes = Tree::new(format!("{} MemoryAP", address.ap_v1()?));
-
-                    if *device_enabled {
-                        match handle_memory_ap(&ap, *debug_base_address, interface) {
-                            Ok(component_tree) => ap_nodes.push(component_tree),
-                            Err(e) => ap_nodes.push(format!("Error during access: {e}")),
-                        };
-                    } else {
-                        ap_nodes.push("Access disabled".to_string());
-                    }
-
-                    tree.push(ap_nodes);
-                }
-
-                ApInformation::Other { address, idr } => {
-                    let jep = idr.DESIGNER;
+        for ap_address in access_ports {
+            use probe_rs::architecture::arm::ap::IDR;
+            let idr: IDR = interface
+                .read_raw_ap_register(&ap_address, IDR::ADDRESS)?
+                .try_into()?;
+
+            if idr.CLASS == ApClass::MemAp {
+                let mut ap_nodes = Tree::new(format!("{} MemoryAP", ap_address.ap_v1()?));
+                match handle_memory_ap(interface, &ap_address) {
+                    Ok(component_tree) => ap_nodes.push(component_tree),
+                    Err(e) => ap_nodes.push(format!("Error during access: {e}")),
+                };
+                tree.push(ap_nodes);
+            } else {
+                let jep = idr.DESIGNER;
 
-                    let ap_type = if idr.DESIGNER == JEP_ARM {
-                        format!("{:?}", idr.TYPE)
-                    } else {
-                        format!("{:#x}", idr.TYPE as u8)
-                    };
+                let ap_type = if idr.DESIGNER == JEP_ARM {
+                    format!("{:?}", idr.TYPE)
+                } else {
+                    format!("{:#x}", idr.TYPE as u8)
+                };
 
-                    tree.push(format!(
+                tree.push(format!(
                     "{} Unknown AP (Designer: {}, Class: {:?}, Type: {}, Variant: {:#x}, Revision: {:#x})",
-                    address.ap_v1()?,
+                    ap_address.ap_v1()?,
                     jep.get().unwrap_or("<unknown>"),
                     idr.CLASS,
                     ap_type,
                     idr.VARIANT,
                     idr.REVISION
                 ));
-                }
             }
         }
 
@@ -350,12 +338,12 @@ fn show_arm_info(interface: &mut dyn ArmProbeInterface, dp: DpAddress) -> Result
 }
 
 fn handle_memory_ap(
-    access_port: &FullyQualifiedApAddress,
-    base_address: u64,
     interface: &mut dyn ArmProbeInterface,
+    access_port: &FullyQualifiedApAddress,
 ) -> Result<Tree<String>, anyhow::Error> {
     let component = {
         let mut memory = interface.memory_interface(access_port)?;
+        let base_address = memory.base_address()?;
         let mut demcr = Demcr(memory.read_word_32(Demcr::get_mmio_address())?);
         demcr.set_dwtena(true);
         memory.write_word_32(Demcr::get_mmio_address(), demcr.into())?;

probe-rs-tools/src/bin/probe-rs/cmd/info.rs

@@ -106,6 +106,7 @@ clap = { version = "4", features = ["derive"] }
 itm = { version = "0.9.0-rc.1", default-features = false }
 pretty_assertions = "1"
 test-case = "3"
+test-log = { version = "0.2.16", features = [ "trace" ] }
 termtree = "0.4"
 insta = { version = "1.38", default-features = false, features = ["yaml"] }
 

probe-rs/Cargo.toml

@@ -1,9 +1,6 @@
 //! Generic access port
 
-use super::{AccessPortType, ApRegister, Register};
-use crate::architecture::arm::{
-    communication_interface::RegisterParseError, FullyQualifiedApAddress,
-};
+use crate::architecture::arm::communication_interface::RegisterParseError;
 
 /// Describes the class of an access port defined in the [`ARM Debug Interface v5.2`](https://developer.arm.com/documentation/ihi0031/f/?lang=en) specification.
 #[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
@@ -39,14 +36,14 @@ pub enum ApType {
     JtagComAp = 0x0,
     /// A AMBA based AHB3 AP (see E1.5).
     AmbaAhb3 = 0x1,
-    /// A AMBA based AHB2 and AHB3 AP (see E1.8).
-    AmbaAhb2Ahb3 = 0x2,
+    /// A AMBA based APB2 and APB3 AP (see E1.8).
+    AmbaApb2Apb3 = 0x2,
     /// A AMBA based AXI3 and AXI4 AP (see E1.2).
     AmbaAxi3Axi4 = 0x4,
     /// A AMBA based AHB5 AP (see E1.6).
     AmbaAhb5 = 0x5,
-    /// A AMBA based AHB4 AP (see E1.3).
-    AmbaAhb4 = 0x6,
+    /// A AMBA based APB4 and APB5 AP (see E1.3).
+    AmbaApb4Apb5 = 0x6,
     /// A AMBA based AXI5 AP (see E1.4).
     AmbaAxi5 = 0x7,
     /// A AMBA based protected AHB5 AP (see E1.7).
@@ -59,25 +56,18 @@ impl ApType {
         match value {
             0x0 => Some(ApType::JtagComAp),
             0x1 => Some(ApType::AmbaAhb3),
-            0x2 => Some(ApType::AmbaAhb2Ahb3),
+            0x2 => Some(ApType::AmbaApb2Apb3),
             0x4 => Some(ApType::AmbaAxi3Axi4),
             0x5 => Some(ApType::AmbaAhb5),
-            0x6 => Some(ApType::AmbaAhb4),
+            0x6 => Some(ApType::AmbaApb4Apb5),
             0x7 => Some(ApType::AmbaAxi5),
             0x8 => Some(ApType::AmbaAhb5Hprot),
             _ => None,
         }
     }
 }
 
-define_ap!(
-    /// A generic access port which implements just the register every access port has to implement
-    /// to be compliant with the ADI 5.2 specification.
-    GenericAp
-);
-
 define_ap_register!(
-    type: GenericAp,
     /// Identification Register
     ///
     /// The identification register is used to identify