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psun3xwenlingz
psun3x
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wenlingz
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DM: gvt: Identical mapping for GPU DSM refine to support EHL/TGL
Windows graphic driver obtains DSM address from in-BAR mmio register which has passthroughed. Not like the other platforms obtained from pci configure space register which has virtualized. GPU GuC must use WOPCM in DSM, besides, Windows OS wants to manage DSM also. These two reason force acrn has to keep identical mapping to avoid trap mmio BAR to do the emulation. Tracked-On: #5880 Signed-off-by: Peng Sun <[email protected]>
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7 files changed

+147
-110
lines changed

7 files changed

+147
-110
lines changed

‎devicemodel/core/sw_load_common.c‎

Lines changed: 71 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -54,20 +54,14 @@ static char bootargs[BOOT_ARG_LEN];
5454
* Begin Limit Type Length
5555
* 0: 0 - 0xA0000 RAM 0xA0000
5656
* 1: 0x100000 - lowmem part1 RAM 0x0
57-
* 2: gpu_rsvd_bot - gpu_rsvd_top (reserved) 0x4004000
58-
* 3: lowmem part2 - 0x7f800000 (reserved) 0x0
59-
* 4: SW SRAM_bot - 0x80000000 (reserved) SOFTWARE_SRAM_MAX_SIZE
60-
* 5: 0xDB000000 - 0xDF000000 (reserved) 64MB
61-
* 6: 0xDF000000 - 0xE0000000 (reserved) 16MB
62-
* 7: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB
63-
* 8: 0x140000000 - highmem RAM highmem - 5GB
57+
* 2: SW SRAM_bot - SW SRAM_top (reserved) SOFTWARE_SRAM_MAX_SIZE
58+
* 3: gpu_rsvd_bot - gpu_rsvd_top (reserved) 0x4004000
59+
* 4: lowmem part2 - 0x80000000 (reserved) 0x0
60+
* 5: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB
61+
* 6: 0x140000000 - highmem RAM highmem - 5GB
6462
*
6563
* FIXME: Do we need to reserve DSM and OPREGION for GVTD here.
6664
*/
67-
68-
#define GPU_DSM_OPREGION_BASE_GPA 0x3B800000
69-
#define GPU_DSM_OPREGION_SIZE 0x4004000
70-
7165
const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
7266
{ /* 0 to video memory */
7367
.baseaddr = 0x00000000,
@@ -81,30 +75,30 @@ const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
8175
.type = E820_TYPE_RAM
8276
},
8377

84-
{ /* TGL GPU DSM & OpRegion area */
85-
.baseaddr = GPU_DSM_OPREGION_BASE_GPA,
86-
.length = GPU_DSM_OPREGION_SIZE,
87-
.type = E820_TYPE_RESERVED
88-
},
89-
90-
{ /* lowmem part2 to lowmem_limit */
91-
.baseaddr = GPU_DSM_OPREGION_BASE_GPA + GPU_DSM_OPREGION_SIZE,
92-
.length = 0x0,
93-
.type = E820_TYPE_RESERVED
94-
},
95-
9678
/*
97-
* Software SRAM area: base: 0x7f800000, size: 0x800000
79+
* Software SRAM area: size: 0x800000
9880
* In native, the Software SRAM region should be part of DRAM memory.
9981
* But one fixed Software SRAM gpa is friendly for virtualization due
10082
* to decoupled with various guest memory size.
10183
*/
10284
{
103-
.baseaddr = SOFTWARE_SRAM_BASE_GPA,
104-
.length = SOFTWARE_SRAM_MAX_SIZE,
85+
.baseaddr = 0x0,
86+
.length = 0x0,
10587
.type = E820_TYPE_RESERVED
10688
},
10789

90+
{ /* GPU DSM & OpRegion reserved region */
91+
.baseaddr = 0x0,
92+
.length = 0x0,
93+
.type = E820_TYPE_RESERVED
94+
},
95+
96+
{ /* lowmem part2 to lowmem_limit */
97+
.baseaddr = 0x0,
98+
.length = 0x0,
99+
.type = E820_TYPE_RESERVED
100+
},
101+
108102
{ /* ECFG_BASE to 4GB */
109103
.baseaddr = PCI_EMUL_ECFG_BASE,
110104
.length = (4 * GB) - PCI_EMUL_ECFG_BASE,
@@ -225,32 +219,65 @@ uint32_t
225219
acrn_create_e820_table(struct vmctx *ctx, struct e820_entry *e820)
226220
{
227221
uint32_t removed = 0, k;
222+
uint32_t gpu_rsvmem_base_gpa = 0;
223+
uint64_t software_sram_base_gpa = 0;
228224

229225
memcpy(e820, e820_default_entries, sizeof(e820_default_entries));
230-
if (ctx->lowmem <= e820[LOWRAM_E820_ENTRY + 2].baseaddr) {
231-
e820[LOWRAM_E820_ENTRY].length =
232-
(ctx->lowmem < e820[LOWRAM_E820_ENTRY+1].baseaddr ? ctx->lowmem :
233-
e820[LOWRAM_E820_ENTRY+1].baseaddr) - e820[LOWRAM_E820_ENTRY].baseaddr;
234226

235-
memmove(&e820[LOWRAM_E820_ENTRY + 2], &e820[LOWRAM_E820_ENTRY + 3],
236-
sizeof(struct e820_entry) *
237-
(NUM_E820_ENTRIES - (LOWRAM_E820_ENTRY + 3)));
238-
removed++;
227+
/* FIXME: Here wastes 8MB memory if pSRAM is enabled, and 64MB+16KB if
228+
* GPU reserved memory is exist.
229+
*
230+
* Determines the GPU region due to DSM identical mapping.
231+
*/
232+
gpu_rsvmem_base_gpa = get_gpu_rsvmem_base_gpa();
233+
if (gpu_rsvmem_base_gpa) {
234+
e820[LOWRAM_E820_ENTRY + 2].baseaddr = gpu_rsvmem_base_gpa;
235+
e820[LOWRAM_E820_ENTRY + 2].length = get_gpu_rsvmem_size();
239236
} else {
240-
e820[LOWRAM_E820_ENTRY].length = e820[LOWRAM_E820_ENTRY+1].baseaddr -
241-
e820[LOWRAM_E820_ENTRY].baseaddr;
237+
e820[LOWRAM_E820_ENTRY + 2].baseaddr = ctx->lowmem_limit;
238+
}
242239

243-
e820[LOWRAM_E820_ENTRY + 2].length =
244-
((ctx->lowmem < e820[LOWRAM_E820_ENTRY + 3].baseaddr) ? ctx->lowmem :
245-
e820[LOWRAM_E820_ENTRY + 3].baseaddr) - e820[LOWRAM_E820_ENTRY + 2].baseaddr;
240+
/* Always put SW SRAM before GPU region and keep 1MB boundary for protection. */
241+
software_sram_base_gpa = get_software_sram_base_gpa();
242+
if (software_sram_base_gpa) {
243+
e820[LOWRAM_E820_ENTRY + 1].baseaddr = software_sram_base_gpa;
244+
e820[LOWRAM_E820_ENTRY + 1].length = get_software_sram_size();
245+
} else {
246+
e820[LOWRAM_E820_ENTRY + 1].baseaddr = e820[LOWRAM_E820_ENTRY + 2].baseaddr;
246247
}
247248

248-
/* remove [5GB, highmem) if it's empty */
249-
if (ctx->highmem > 0) {
250-
e820[HIGHRAM_E820_ENTRY - removed].type = E820_TYPE_RAM;
251-
e820[HIGHRAM_E820_ENTRY - removed].length = ctx->highmem;
249+
if (ctx->lowmem <= e820[LOWRAM_E820_ENTRY + 1].baseaddr) {
250+
/* Caculation for lowmem part1 */
251+
e820[LOWRAM_E820_ENTRY].length =
252+
ctx->lowmem - e820[LOWRAM_E820_ENTRY].baseaddr;
252253
} else {
253-
removed++;
254+
/* Caculation for lowmem part1 */
255+
e820[LOWRAM_E820_ENTRY].length =
256+
e820[LOWRAM_E820_ENTRY + 1].baseaddr - e820[LOWRAM_E820_ENTRY].baseaddr;
257+
/* Caculation for lowmem part2 */
258+
e820[LOWRAM_E820_ENTRY + 3].baseaddr =
259+
e820[LOWRAM_E820_ENTRY + 2].baseaddr + e820[LOWRAM_E820_ENTRY + 2].length;
260+
if (ctx->lowmem > e820[LOWRAM_E820_ENTRY + 3].baseaddr) {
261+
e820[LOWRAM_E820_ENTRY + 3].length =
262+
ctx->lowmem - e820[LOWRAM_E820_ENTRY + 3].baseaddr;
263+
e820[LOWRAM_E820_ENTRY + 3].type = E820_TYPE_RAM;
264+
}
265+
}
266+
267+
/* Caculation for highmem */
268+
if (ctx->highmem > 0) {
269+
e820[HIGHRAM_E820_ENTRY].type = E820_TYPE_RAM;
270+
e820[HIGHRAM_E820_ENTRY].length = ctx->highmem;
271+
}
272+
273+
/* Remove empty entries in e820 table */
274+
for (k = 0; k < (NUM_E820_ENTRIES - 1 - removed); k++) {
275+
if (e820[k].length == 0x0) {
276+
memmove(&e820[k], &e820[k + 1], sizeof(struct e820_entry) *
277+
(NUM_E820_ENTRIES - (k + 1)));
278+
k--;
279+
removed++;
280+
}
254281
}
255282

256283
pr_info("SW_LOAD: build e820 %d entries to addr: %p\r\n",

‎devicemodel/hw/pci/passthrough.c‎

Lines changed: 15 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -59,48 +59,13 @@
5959

6060
#define PCI_BDF_GPU 0x00000010 /* 00:02.0 */
6161

62-
/* Reserved region in e820 table for GVT
63-
* for GVT-g use:
64-
* [0xDF000000, 0xDF800000) 8M, GOP FB, used OvmfPkg/GvtGopDxe for 1080p@30
65-
* [0xDFFFD000, 0xDFFFF000) 8K, OpRegion, used by GvtGopDxe and GVT-g
66-
* [0xDFFFF000, 0XE0000000) 4K, Reserved, not used
67-
* for TGL GVT-d use:
68-
* [0x3B800000, 0x3F800000) 64M, Date Stolen Memory
69-
* [0x3F800000, 0X3F804000] 16K, OpRegion and Extended OpRegion
70-
* for EHL/WHL/KBL GVT-d use:
71-
* [0xDB000000, 0xDF000000) 64M, DSM, used by native GOP and gfx driver
72-
* [0xDFFFC000, 0xDFFFE000) 8K, OpRegion, used by native GOP and gfx driver
73-
* [0xDFFFE000, 0XE0000000] 8K, Extended OpRegion, store raw VBT
74-
* OpRegion: 8KB(0x2000)
75-
* [ OpRegion Header ] Offset: 0x0
76-
* [ Mailbox #1: ACPI ] Offset: 0x100
77-
* [ Mailbox #2: SWSCI ] Offset: 0x200
78-
* [ Mailbox #3: ASLE ] Offset: 0x300
79-
* [ Mailbox #4: VBT ] Offset: 0x400
80-
* [ Mailbox #5: ASLE EXT ] Offset: 0x1C00
81-
* Extended OpRegion: 8KB(0x2000)
82-
* [ Raw VBT ] Offset: 0x0
83-
* If VBT <= 6KB, stores in Mailbox #4
84-
* If VBT > 6KB, stores in Extended OpRegion
85-
* ASLE.rvda stores the location of VBT.
86-
* For OpRegion 2.1+: ASLE.rvda = offset to OpRegion base address
87-
* For OpRegion 2.0: ASLE.rvda = physical address, not support currently
88-
*/
89-
#define GPU_DSM_GPA 0xDB000000
90-
#define GPU_DSM_SIZE 0x4000000
91-
#define GPU_OPREGION_GPA 0xDFFFC000
92-
#define GPU_OPREGION_SIZE 0x4000
93-
/*
94-
* TODO: Forced DSM/OPREGION size requires native BIOS configuration.
95-
* This limitation need remove in future
96-
*/
62+
extern uint64_t audio_nhlt_len;
63+
9764
uint32_t gpu_dsm_hpa = 0;
9865
uint32_t gpu_dsm_gpa = 0;
9966
uint32_t gpu_opregion_hpa = 0;
10067
uint32_t gpu_opregion_gpa = 0;
10168

102-
extern uint64_t audio_nhlt_len;
103-
10469
/* reference count for libpciaccess init/deinit */
10570
static int pciaccess_ref_cnt;
10671
static pthread_mutex_t ref_cnt_mtx = PTHREAD_MUTEX_INITIALIZER;
@@ -472,6 +437,18 @@ has_virt_pcicfg_regs_on_def_gpu(int offset)
472437
return ((offset == PCIR_BDSM) || (offset == PCIR_ASLS_CTL));
473438
}
474439

440+
uint32_t
441+
get_gpu_rsvmem_base_gpa()
442+
{
443+
return gpu_opregion_gpa;
444+
}
445+
446+
uint32_t
447+
get_gpu_rsvmem_size()
448+
{
449+
return GPU_OPREGION_SIZE + GPU_DSM_SIZE;
450+
}
451+
475452
/*
476453
* passthrough GPU DSM(Data Stolen Memory) and Opregion to guest
477454
*/
@@ -487,24 +464,6 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
487464

488465
switch (device) {
489466
case INTEL_ELKHARTLAKE:
490-
/* BDSM register has 64 bits.
491-
* bits 63:20 contains the base address of stolen memory
492-
*/
493-
gpu_dsm_hpa = read_config(ptdev->phys_dev, PCIR_GEN11_BDSM_DW0, 4);
494-
dsm_mask_val = gpu_dsm_hpa & ~PCIM_BDSM_MASK;
495-
gpu_dsm_hpa &= PCIM_BDSM_MASK;
496-
gpu_dsm_hpa |= (uint64_t)read_config(ptdev->phys_dev, PCIR_GEN11_BDSM_DW1, 4) << 32;
497-
gpu_dsm_gpa = GPU_DSM_GPA;
498-
499-
pci_set_cfgdata32(ptdev->dev, PCIR_GEN11_BDSM_DW0, gpu_dsm_gpa | dsm_mask_val);
500-
/* write 0 to high 32-bits of BDSM on EHL platform */
501-
pci_set_cfgdata32(ptdev->dev, PCIR_GEN11_BDSM_DW1, 0);
502-
503-
gpu_opregion_gpa = GPU_OPREGION_GPA;
504-
505-
ptdev->has_virt_pcicfg_regs = &has_virt_pcicfg_regs_on_ehl_gpu;
506-
break;
507-
508467
case INTEL_TIGERLAKE:
509468
/* BDSM register has 64 bits.
510469
* bits 63:20 contains the base address of stolen memory
@@ -523,8 +482,6 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
523482
/* write 0 to high 32-bits of BDSM on EHL platform */
524483
pci_set_cfgdata32(ptdev->dev, PCIR_GEN11_BDSM_DW1, 0);
525484

526-
gpu_opregion_gpa = gpu_dsm_gpa + GPU_DSM_SIZE;
527-
528485
ptdev->has_virt_pcicfg_regs = &has_virt_pcicfg_regs_on_ehl_gpu;
529486
break;
530487
/* If on default platforms, such as KBL,WHL */
@@ -537,12 +494,11 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
537494

538495
pci_set_cfgdata32(ptdev->dev, PCIR_BDSM, gpu_dsm_gpa | dsm_mask_val);
539496

540-
gpu_opregion_gpa = GPU_OPREGION_GPA;
541-
542497
ptdev->has_virt_pcicfg_regs = &has_virt_pcicfg_regs_on_def_gpu;
543498
break;
544499
}
545500

501+
gpu_opregion_gpa = gpu_dsm_gpa - GPU_OPREGION_SIZE;
546502
pci_set_cfgdata32(ptdev->dev, PCIR_ASLS_CTL, gpu_opregion_gpa | (opregion_phys & ~PCIM_ASLS_OPREGION_MASK));
547503

548504
/* initialize the EPT mapping for passthrough GPU dsm region */

‎devicemodel/hw/platform/acpi/acpi.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1095,13 +1095,13 @@ int create_and_inject_vrtct(struct vmctx *ctx)
10951095
uint8_t *vrtct;
10961096
struct vm_memmap memmap = {
10971097
.type = VM_MMIO,
1098-
.gpa = SOFTWARE_SRAM_BASE_GPA,
10991098
/* HPA base and size of Software SRAM shall be parsed from vRTCT. */
11001099
.hpa = 0,
11011100
.len = 0,
11021101
.prot = PROT_ALL
11031102
};
11041103

1104+
memmap.gpa = get_software_sram_base_gpa();
11051105
native_rtct_fd = open(RTCT_NATIVE_FILE_PATH_IN_SOS, O_RDONLY);
11061106
if (native_rtct_fd < 0) {
11071107
pr_err("failed to open /sys/firmware/acpi/tables/PTCT !!!!! errno:%d\n", errno);

‎devicemodel/hw/platform/acpi/rtct.c‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@
3535

3636
static uint64_t software_sram_base_hpa;
3737
static uint64_t software_sram_size;
38+
static uint64_t software_sram_base_gpa;
3839

3940
static uint8_t vrtct_checksum(uint8_t *vrtct, uint32_t length)
4041
{
@@ -209,7 +210,7 @@ static void remap_software_sram_regions(struct acpi_table_hdr *vrtct)
209210
foreach_rtct_entry(vrtct, entry) {
210211
if (entry->type == RTCT_ENTRY_TYPE_PSRAM) {
211212
sw_sram_region = (struct rtct_entry_data_psram *)entry->data;
212-
sw_sram_region->base = SOFTWARE_SRAM_BASE_GPA + (sw_sram_region->base - hpa_bottom);
213+
sw_sram_region->base = software_sram_base_gpa + (sw_sram_region->base - hpa_bottom);
213214
}
214215
}
215216
}
@@ -287,6 +288,11 @@ uint64_t get_software_sram_base_hpa(void)
287288
return software_sram_base_hpa;
288289
}
289290

291+
uint64_t get_software_sram_base_gpa(void)
292+
{
293+
return software_sram_base_gpa;
294+
}
295+
290296
uint64_t get_software_sram_size(void)
291297
{
292298
return software_sram_size;
@@ -306,6 +312,7 @@ uint8_t *build_vrtct(struct vmctx *ctx, void *cfg)
306312
struct acrn_vm_config vm_cfg;
307313
struct acpi_table_hdr *rtct_cfg, *vrtct = NULL;
308314
uint64_t dm_cpu_bitmask, hv_cpu_bitmask, guest_pcpu_bitmask;
315+
uint32_t gpu_rsvmem_base_gpa = 0;
309316

310317
if ((cfg == NULL) || (ctx == NULL))
311318
return NULL;
@@ -351,6 +358,14 @@ uint8_t *build_vrtct(struct vmctx *ctx, void *cfg)
351358
pr_info("%s, dm_cpu_bitmask:0x%x, hv_cpu_bitmask:0x%x, guest_cpu_bitmask: 0x%x\n",
352359
__func__, dm_cpu_bitmask, hv_cpu_bitmask, guest_pcpu_bitmask);
353360

361+
gpu_rsvmem_base_gpa = get_gpu_rsvmem_base_gpa();
362+
software_sram_size = SOFTWARE_SRAM_MAX_SIZE;
363+
/* TODO: It is better to put one boundary between GPU region and SW SRAM
364+
* for protection.
365+
*/
366+
software_sram_base_gpa = ((gpu_rsvmem_base_gpa ? gpu_rsvmem_base_gpa : 0x80000000UL) -
367+
software_sram_size) & ~software_sram_size;
368+
354369
if (passthru_rtct_to_guest(vrtct, rtct_cfg, guest_pcpu_bitmask)) {
355370
pr_err("%s, initialize vRTCT fail.", __func__);
356371
goto error;

‎devicemodel/include/pci_core.h‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -263,6 +263,45 @@ int create_mmio_rsvd_rgn(uint64_t start,
263263
uint64_t end, int idx, int bar_type, struct pci_vdev *vdev);
264264
void destory_mmio_rsvd_rgns(struct pci_vdev *vdev);
265265

266+
/* Reserved region in e820 table for GVT
267+
* for GVT-g use:
268+
* [0xDF000000, 0xDF800000) 8M, GOP FB, used OvmfPkg/GvtGopDxe for 1080p@30
269+
* [0xDFFFD000, 0xDFFFF000) 8K, OpRegion, used by GvtGopDxe and GVT-g
270+
* [0xDFFFF000, 0XE0000000) 4K, Reserved, not used
271+
* for TGL/EHL GVT-d use: identical mapping, same with host layout
272+
* [gpu_opregion_hpa, gpu_opregion_hpa+size) 16K, OpRegion and Extended OpRegion
273+
* [gpu_dsm_hpa, gpu_dsm_hpa+size] 64M, Date Stolen Memory
274+
* for WHL/KBL GVT-d use:
275+
* [0x7BFFC000, 0x7BFFE000) 8K, OpRegion, used by native GOP and gfx driver
276+
* [0x7BFFE000, 0X7C000000] 8K, Extended OpRegion, store raw VBT
277+
* [0x7C000000, 0x80000000] 64M, DSM, used by native GOP and gfx driver
278+
* OpRegion: 8KB(0x2000)
279+
* [ OpRegion Header ] Offset: 0x0
280+
* [ Mailbox #1: ACPI ] Offset: 0x100
281+
* [ Mailbox #2: SWSCI ] Offset: 0x200
282+
* [ Mailbox #3: ASLE ] Offset: 0x300
283+
* [ Mailbox #4: VBT ] Offset: 0x400
284+
* [ Mailbox #5: ASLE EXT ] Offset: 0x1C00
285+
* Extended OpRegion: 8KB(0x2000)
286+
* [ Raw VBT ] Offset: 0x0
287+
* If VBT <= 6KB, stores in Mailbox #4
288+
* If VBT > 6KB, stores in Extended OpRegion
289+
* ASLE.rvda stores the location of VBT.
290+
* For OpRegion 2.1+: ASLE.rvda = offset to OpRegion base address
291+
* For OpRegion 2.0: ASLE.rvda = physical address, not support currently
292+
*/
293+
#define GPU_DSM_GPA 0x7C000000
294+
#define GPU_DSM_SIZE 0x4000000
295+
#define GPU_OPREGION_SIZE 0x4000
296+
/*
297+
* TODO: Forced DSM/OPREGION size requires native BIOS configuration.
298+
* This limitation need remove in future
299+
*/
300+
uint32_t get_gpu_rsvmem_base_gpa(void);
301+
uint32_t get_gpu_rsvmem_size(void);
302+
uint64_t get_software_sram_base_gpa(void);
303+
uint64_t get_software_sram_size(void);
304+
266305
typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
267306
int ioapic_irq, void *arg);
268307

‎devicemodel/include/pcireg.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1066,8 +1066,8 @@
10661066
#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */
10671067

10681068
/* Graphics definitions */
1069-
#define INTEL_ELKHARTLAKE 0x4551
1070-
#define INTEL_TIGERLAKE 0x9a49
1069+
#define INTEL_ELKHARTLAKE 0x4571
1070+
#define INTEL_TIGERLAKE 0x9a49
10711071
#define PCIR_BDSM 0x5C /* BDSM graphics base data of stolen memory register */
10721072
#define PCIR_GEN11_BDSM_DW0 0xC0
10731073
#define PCIR_GEN11_BDSM_DW1 0xC4

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