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Merge pull request #522 from uyjulian/sif_modules
sifman, sifcmd, sifinit implementations
2 parents 247f143 + 0a49ebb commit fa86186

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‎common/include/iop_mmio_hwport.h‎

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/*
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# _____ ___ ____ ___ ____
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# ____| | ____| | | |____|
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# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
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#-----------------------------------------------------------------------
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# Copyright ps2dev - http://www.ps2dev.org
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# Licenced under Academic Free License version 2.0
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# Review ps2sdk README & LICENSE files for further details.
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*/
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/**
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* @file
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* Definitions for memory-mapped I/O for IOP.
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*/
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#ifndef __IOP_MMIO_HWPORT__
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#define __IOP_MMIO_HWPORT__
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typedef struct dmac_channel_
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{
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vu32 madr;
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vu32 bcr;
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vu32 chcr;
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vu32 tadr;
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} dmac_channel_t;
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typedef struct dmac1_mmio_hwport_
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{
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dmac_channel_t oldch[7];
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vu32 dpcr1;
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vu32 dicr1;
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} dmac1_mmio_hwport_t;
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typedef struct dmac2_mmio_hwport_
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{
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dmac_channel_t newch[6];
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dmac_channel_t new_unusedch;
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vu32 dpcr2;
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vu32 dicr2;
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vu32 dmacen;
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vu32 dmacinten;
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} dmac2_mmio_hwport_t;
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typedef struct dmac_channel3_
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{
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vu32 madr;
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vu32 dlen;
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vu32 slice;
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vu32 chcr;
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vu32 rtar;
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vu32 DmarReadStart;
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vu32 DmarReadEnd;
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} dmac_channel3_t;
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typedef struct dmac3_mmio_hwport_
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{
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dmac_channel3_t dmac_channel3_0;
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u8 unused_1c[0x4];
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dmac_channel3_t dmac_channel3_1;
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u8 unused_3c[0x4];
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dmac_channel3_t dmac_channel3_2;
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vu32 DmarWriteStart;
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vu32 DmarWriteEnd;
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u8 unused_64[0x1C];
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} dmac3_mmio_hwport_t;
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typedef struct ssbus1_mmio_hwport_
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{
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vu32 ind_0_address;
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vu32 ind_8_address;
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vu32 ind_0_delay;
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vu32 ind_1_delay;
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vu32 ind_2_delay;
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vu32 ind_4_delay;
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vu32 ind_5_delay;
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vu32 ind_8_delay;
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vu32 common_delay;
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} ssbus1_mmio_hwport_t;
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typedef struct ssbus2_mmio_hwport_
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{
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vu32 ind_1_address;
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vu32 ind_4_address;
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vu32 ind_5_address;
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vu32 ind_9_address;
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vu32 ind_B_address;
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vu32 ind_9_delay;
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vu32 ind_A_delay;
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vu32 ind_B_delay;
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vu32 ind_C_delay;
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} ssbus2_mmio_hwport_t;
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typedef struct sio0_1_mmio_hwport_
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{
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vu32 data;
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vu32 stat;
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vu16 mode;
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vu16 ctrl;
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vu16 misc;
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vu16 baud;
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} sio0_1_mmio_hwport_t;
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typedef struct sio2_mmio_hwport_
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{
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vu8 send3_buf[0x40];
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vu8 send1_2_buf[0x20];
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vu32 out_fifo; /* PCSX2 says in */
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vu32 in_fifo; /* PCSX2 says out */
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vu32 ctrl;
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vu32 recv1;
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vu32 recv2;
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vu32 recv3;
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vu32 unk_78;
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vu32 unk_7c;
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vu32 stat;
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u8 unused[0x7c];
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} sio2_mmio_hwport_t;
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typedef struct usb_mmio_hwport_
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{
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vu32 HcRevision;
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vu32 HcControl;
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vu32 HcCommandStatus;
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vu32 HcInterruptStatus;
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vu32 HcInterruptEnable;
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vu32 HcInterruptDisable;
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vu32 HcHCCA;
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vu32 HcPeriodCurrentEd;
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vu32 HcControlHeadEd;
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vu32 HcControlCurrentEd;
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vu32 HcBulkHeadEd;
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vu32 HcBulkCurrentEd;
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vu32 HcDoneHead;
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vu32 HcFmInterval;
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vu32 HcFmRemaining;
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vu32 HcFmNumber;
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vu32 HcPeriodicStart;
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vu32 HcLsThreshold;
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vu32 HcRhDescriptorA;
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vu32 HcRhDescriptorB;
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vu32 HcRhStatus;
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vu32 HcRhPortStatus[2]; /* PCSX2 says 15 or 11 */
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u8 unused[0xa4];
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} usb_mmio_hwport_t;
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typedef struct ieee1394_mmio_hwport_
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{
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vu32 NodeID;
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vu32 CycleTime;
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vu32 ctrl0;
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vu32 ctrl1;
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vu32 ctrl2;
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vu32 PHYAccess;
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vu32 UnknownRegister18;
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vu32 UnknownRegister1C;
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vu32 intr0;
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vu32 intr0Mask;
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vu32 intr1;
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vu32 intr1Mask;
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vu32 intr2;
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vu32 intr2Mask;
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vu32 dmar;
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vu32 ack_status;
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vu32 ubufTransmitNext;
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vu32 ubufTransmitLast;
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vu32 ubufTransmitClear;
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vu32 ubufReceiveClear;
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vu32 ubufReceive;
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vu32 ubufReceiveLevel;
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vu32 unmapped1[0x06];
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vu32 UnknownRegister70;
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vu32 UnknownRegister74;
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vu32 UnknownRegister78;
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vu32 UnknownRegister7C;
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vu32 PHT_ctrl_ST_R0;
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vu32 PHT_split_TO_R0;
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vu32 PHT_ReqResHdr0_R0;
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vu32 PHT_ReqResHdr1_R0;
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vu32 PHT_ReqResHdr2_R0;
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vu32 STRxNIDSel0_R0;
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vu32 STRxNIDSel1_R0;
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vu32 STRxHDR_R0;
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vu32 STTxHDR_R0;
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vu32 DTransCTRL0;
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vu32 CIPHdrTx0_R0;
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vu32 CIPHdrTx1_R0;
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vu32 padding4;
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vu32 STTxTimeStampOffs_R0;
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vu32 dmaCtrlSR0;
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vu32 dmaTransTRSH0;
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vu32 dbufFIFO_lvlR0;
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vu32 dbufTxDataR0;
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vu32 dbufRxDataR0;
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vu32 dbufWatermarksR0;
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vu32 dbufFIFOSzR0;
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vu32 unmapped2[0x0B];
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vu32 PHT_ctrl_ST_R1;
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vu32 PHT_split_TO_R1;
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vu32 PHT_ReqResHdr0_R1;
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vu32 PHT_ReqResHdr1_R1;
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vu32 PHT_ReqResHdr2_R1;
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vu32 STRxNIDSel0_R1;
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vu32 STRxNIDSel1_R1;
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vu32 STRxHDR_R1;
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vu32 STTxHDR_R1;
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vu32 DTransCTRL1;
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vu32 CIPHdrTx0_R1;
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vu32 CIPHdrTx1_R1;
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vu32 padding5;
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vu32 STTxTimeStampOffs_R1;
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vu32 dmaCtrlSR1;
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vu32 dmaTransTRSH1;
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vu32 dbufFIFO_lvlR1;
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vu32 dbufTxDataR1;
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vu32 dbufRxDataR1;
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vu32 dbufWatermarksR1;
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vu32 dbufFIFOSzR1;
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} ieee1394_mmio_hwport_t;
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typedef struct iop_counter_mmio_hwport_
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{
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vu32 count;
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vu32 mode;
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vu32 target;
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vu32 unused_c;
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} iop_counter_mmio_hwport_t;
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typedef struct iop_mmio_hwport_ /* base -> 0xBF800000 */
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{
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u8 scratchpad_cache0[0x400];
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u8 scratchpad_cache1[0x400];
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u8 unv_0800[0x800];
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ssbus1_mmio_hwport_t ssbus1; /* 0x1000 */
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u8 unv_1024[0x1c];
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sio0_1_mmio_hwport_t sio0;
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sio0_1_mmio_hwport_t sio1;
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vu32 iop_ram_size;
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u8 unv_1064[0xC];
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vu32 istat;
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vu32 imask;
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vu32 iop_sbus_info;
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vu32 unk_107c;
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dmac1_mmio_hwport_t dmac1; /* 0x1080 */
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u8 unv_10f8[0x8];
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iop_counter_mmio_hwport_t counter1[3]; /* 0x1100 */
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u8 unv_1130[0x2d0];
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ssbus2_mmio_hwport_t ssbus2; /* 0x1400 */
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u8 unv_1424[0x2c];
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vu32 iop_sbus_ctrl[2]; /* 0x1450 */
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u8 unk_1458[0x8];
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u8 dev9c[0x20];
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iop_counter_mmio_hwport_t counter2[3]; /* 0x1480 */
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u8 unk_14b0[0x10];
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vu32 rtc_holdmode;
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u8 unk_14c4[0x3c];
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dmac2_mmio_hwport_t dmac2; /* 0x1500 */
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dmac3_mmio_hwport_t dmac3; /* 0x1580 */
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usb_mmio_hwport_t usb; /* 0x1600 */
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u8 unk_1700[0x100];
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vu32 ps1_cdrom;
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u8 unk_1804[0xc];
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vu32 ps1_gpu1;
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vu32 ps1_gpu2;
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u8 unk_1818[0x8];
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vu32 ps1_mdec1;
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vu32 ps1_mdec2;
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u8 unk_1828[0x8];
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u8 unk_1830[0xd0];
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u8 deckard_i2c[0x20]; /* 0x1900 */
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u8 unv_1920[0x2e0];
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u8 spu_core0[0x400]; /* 0x1C00 */
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u8 exp2_r2[0x2000]; /* 0x2000 */
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u8 unk_4000[0x4000];
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u8 sio2_internal[0x200]; /* 0x8000 */
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sio2_mmio_hwport_t sio2; /* 0x8200 */
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u8 unk_8300[0x100];
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ieee1394_mmio_hwport_t ieee1394; /* 0x8400 */
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} iop_mmio_hwport_t;
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#if !defined(USE_IOP_MMIO_HWPORT) && defined(_IOP)
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// cppcheck-suppress-macro constVariablePointer
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#define USE_IOP_MMIO_HWPORT() iop_mmio_hwport_t *const iop_mmio_hwport = (iop_mmio_hwport_t *)0xBF800000
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#endif
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#if !defined(USE_IOP_MMIO_HWPORT)
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#define USE_IOP_MMIO_HWPORT()
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#endif
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#endif /* __IOP_MMIO_HWPORT__ */

‎common/include/sif_mmio_hwport.h‎

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/*
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# _____ ___ ____ ___ ____
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# ____| | ____| | | |____|
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# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
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#-----------------------------------------------------------------------
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# Copyright ps2dev - http://www.ps2dev.org
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# Licenced under Academic Free License version 2.0
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# Review ps2sdk README & LICENSE files for further details.
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*/
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/**
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* @file
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* Definitions for memory-mapped I/O for SIF.
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*/
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#ifndef __SIF_MMIO_HWPORT__
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#define __SIF_MMIO_HWPORT__
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typedef struct sif_mmio_hwport_ /* base -> 0xBD000000 */
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{
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vu32 mscom;
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u32 unused04[3];
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vu32 smcom;
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u32 unused14[3];
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vu32 msflag;
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u32 unused24[3];
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vu32 smflag;
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u32 unused34[3];
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vu32 controlreg;
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u32 unused44[7];
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vu32 unk60;
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u32 unused64[3];
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} sif_mmio_hwport_t;
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#if !defined(USE_SIF_MMIO_HWPORT) && defined(_EE)
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// cppcheck-suppress-macro constVariablePointer
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#define USE_SIF_MMIO_HWPORT() \
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sif_mmio_hwport_t *const sif_mmio_hwport = (sif_mmio_hwport_t *)0xB000F200
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#endif
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#if !defined(USE_SIF_MMIO_HWPORT) && defined(_IOP)
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// cppcheck-suppress-macro constVariablePointer
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#define USE_SIF_MMIO_HWPORT() \
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sif_mmio_hwport_t *const sif_mmio_hwport = (sif_mmio_hwport_t *)0xBD000000
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#endif
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#if !defined(USE_SIF_MMIO_HWPORT)
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#define USE_SIF_MMIO_HWPORT()
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#endif
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#endif /* __SIF_MMIO_HWPORT__ */

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