@@ -319,12 +319,6 @@ class I2SDriverESP32V1 {
319319 (i2s_slot_mode_t )cfg.channels );
320320 }
321321
322- i2s_pdm_rx_slot_config_t getRxSlotConfig (I2SConfigESP32V1 &cfg) {
323- return I2S_PDM_RX_SLOT_DEFAULT_CONFIG (
324- (i2s_data_bit_width_t )cfg.bits_per_sample ,
325- (i2s_slot_mode_t )cfg.channels );
326- }
327-
328322 i2s_chan_config_t getChannelConfig (I2SConfigESP32V1 &cfg) {
329323 return I2S_CHANNEL_DEFAULT_CONFIG (
330324 (i2s_port_t )cfg.port_no ,
@@ -335,10 +329,6 @@ class I2SDriverESP32V1 {
335329 return I2S_PDM_TX_CLK_DEFAULT_CONFIG ((uint32_t )cfg.sample_rate );
336330 }
337331
338- i2s_pdm_rx_clk_config_t getRxClockConfig (I2SConfigESP32V1 &cfg) {
339- return I2S_PDM_RX_CLK_DEFAULT_CONFIG ((uint32_t )cfg.sample_rate );
340- }
341-
342332 bool startTX (I2SConfigESP32V1 &cfg, i2s_chan_handle_t &tx_chan, int txPin) {
343333 i2s_pdm_tx_config_t pdm_tx_cfg = {
344334 .clk_cfg = getTxClockConfig (cfg),
@@ -365,6 +355,15 @@ class I2SDriverESP32V1 {
365355 return true ;
366356 }
367357
358+ #if defined(USE_PDM_RX)
359+ i2s_pdm_rx_slot_config_t getRxSlotConfig (I2SConfigESP32V1 &cfg) {
360+ return I2S_PDM_RX_SLOT_DEFAULT_CONFIG (
361+ (i2s_data_bit_width_t )cfg.bits_per_sample ,
362+ (i2s_slot_mode_t )cfg.channels );
363+ }
364+ i2s_pdm_rx_clk_config_t getRxClockConfig (I2SConfigESP32V1 &cfg) {
365+ return I2S_PDM_RX_CLK_DEFAULT_CONFIG ((uint32_t )cfg.sample_rate );
366+ }
368367 bool startRX (I2SConfigESP32V1 &cfg, i2s_chan_handle_t &rx_chan, int rxPin) {
369368 i2s_pdm_rx_config_t pdm_rx_cfg = {
370369 .clk_cfg = getRxClockConfig (cfg),
@@ -390,7 +389,12 @@ class I2SDriverESP32V1 {
390389 }
391390 return true ;
392391 }
393-
392+ #else
393+ bool startRX (I2SConfigESP32V1 &cfg, i2s_chan_handle_t &rx_chan, int rxPin) {
394+ LOGE (" PDM RX not supported" );
395+ return false ;
396+ }
397+ #endif
394398 } pdm;
395399
396400#endif
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