@@ -162,11 +162,10 @@ class I2SDriverESP32V1 {
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i2s_chan_handle_t &rx_chan, int txPin, int rxPin) {
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TRACED ();
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LOGI (" tx: %d, rx: %d" , txPin, rxPin);
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- i2s_std_config_t std_cfg = {
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- .clk_cfg = getClockConfig (cfg),
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- .slot_cfg = getSlotConfig (cfg),
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- .gpio_cfg =
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- {
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+ i2s_std_config_t std_cfg;
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+ std_cfg.clk_cfg = getClockConfig (cfg);
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+ std_cfg.slot_cfg = getSlotConfig (cfg);
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+ std_cfg.gpio_cfg = {
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.mclk = (gpio_num_t )cfg.pin_mck ,
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.bclk = (gpio_num_t )cfg.pin_bck ,
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.ws = (gpio_num_t )cfg.pin_ws ,
@@ -178,8 +177,8 @@ class I2SDriverESP32V1 {
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.bclk_inv = false ,
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.ws_inv = false ,
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},
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- },
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};
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+
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if (cfg.rx_tx_mode == RXTX_MODE || cfg.rx_tx_mode == TX_MODE) {
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if (i2s_channel_init_std_mode (tx_chan, &std_cfg) != ESP_OK) {
@@ -264,8 +263,12 @@ class I2SDriverESP32V1 {
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i2s_std_clk_config_t getClockConfig (I2SConfigESP32V1 &cfg) {
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TRACED ();
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- i2s_std_clk_config_t clk_cfg =
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- I2S_STD_CLK_DEFAULT_CONFIG ((uint32_t )cfg.sample_rate );
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+ i2s_std_clk_config_t clk_cfg;// = I2S_STD_CLK_DEFAULT_CONFIG((uint32_t)cfg.sample_rate);
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+ memset (&clk_cfg, 0 , sizeof (i2s_std_clk_config_t ));
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+ clk_cfg.sample_rate_hz = cfg.sample_rate ;
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+ clk_cfg.clk_src = getClockSource (cfg);
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+ // clk_cfg.ext_clk_freq_hz = 0;
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+
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if (cfg.mclk_multiple > 0 ) {
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clk_cfg.mclk_multiple = (i2s_mclk_multiple_t )cfg.mclk_multiple ;
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LOGI (" mclk_multiple=%d" , clk_cfg.mclk_multiple );
@@ -275,13 +278,11 @@ class I2SDriverESP32V1 {
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clk_cfg.mclk_multiple = I2S_MCLK_MULTIPLE_384;
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LOGI (" mclk_multiple=384" );
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} else {
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+ clk_cfg.mclk_multiple = I2S_MCLK_MULTIPLE_256;
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LOGI (" mclk_multiple=%d" , clk_cfg.mclk_multiple );
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}
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}
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- // determine clock source
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- clk_cfg.clk_src = getClockSource (cfg);
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-
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return clk_cfg;
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}
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