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Fix L3 Transfers
1 parent a03c8cb commit 7262da8

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3 files changed

+21
-6
lines changed

3 files changed

+21
-6
lines changed

Deeploy/Targets/PULPOpen/DMA/L3Dma.py

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,8 @@ class L3DmaFuture(Future):
1616
% if comment:
1717
// ${comment}
1818
% endif
19-
pi_cl_ram_req_t ${name};
19+
pi_cl_ram_req_t ${name} = {0};
20+
2021
""")
2122

2223
_deinitTemplate = NodeTemplate("")
@@ -27,7 +28,9 @@ class L3DmaFuture(Future):
2728
% if comment:
2829
// ${comment}
2930
% endif
30-
pi_cl_ram_copy_wait(&${name});
31+
if (${name}.size != 0) {
32+
pi_cl_ram_copy_wait(&${name});
33+
}
3134
""")
3235

3336

Deeploy/TilingExtension/AsyncDma.py

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -178,9 +178,19 @@ def transfer(self,
178178
future: Future,
179179
comment: str = "") -> Tuple[List[CodeSnippet], List[CodeSnippet], List[CodeSnippet]]:
180180
callStack = []
181-
callStack.extend(
182-
self.dma.transfer(ctxt, externalBuffer, localBuffer, shape, strideExt, strideLoc, direction, future))
181+
alloc_code, dma_code, deinit_code = self.dma.transfer(ctxt,
182+
externalBuffer,
183+
localBuffer,
184+
shape,
185+
strideExt,
186+
strideLoc,
187+
direction,
188+
future,
189+
comment = comment)
190+
callStack.extend(alloc_code)
191+
callStack.extend(dma_code)
183192
callStack.append(future.wait())
193+
callStack.extend(deinit_code)
184194

185195
return [], callStack, []
186196

Deeploy/TilingExtension/CodeTransformationPasses/SingleBufferingTilingCodeGeneration.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
from Deeploy.AbstractDataTypes import VoidType
88
from Deeploy.DeeployTypes import CodeSnippet, ExecutionBlock, NetworkContext, NodeTemplate, OperatorRepresentation, \
99
VariableBuffer, _ReferenceBuffer
10-
from Deeploy.TilingExtension.AsyncDma import AsyncDma, DmaDirection, Future
10+
from Deeploy.TilingExtension.AsyncDma import AsyncDma, DmaDirection, EmptyFuture, Future
1111
from Deeploy.TilingExtension.CodeTransformationPasses.TilingCodeGeneration import TilingCodeGeneration
1212
from Deeploy.TilingExtension.CodeTransformationPasses.TilingHoistingMixIn import dictOfArrays
1313
from Deeploy.TilingExtension.CodeTransformationPasses.TilingPrototypes import ProfilingPrototypeMixIn, \
@@ -66,6 +66,8 @@ def _generateTransferScheduleCalls(self,
6666
override_type = VoidType)
6767

6868
future = self.dma.getFuture(tensorName, direction)
69+
_future = set([future]) - futures
70+
_future = _future.pop() if len(_future) > 0 else EmptyFuture("")
6971
futures.add(future)
7072

7173
callStack.extend(
@@ -76,7 +78,7 @@ def _generateTransferScheduleCalls(self,
7678
localBuffer,
7779
externalBufferRef,
7880
direction,
79-
future,
81+
_future,
8082
comment = comment))
8183

8284
referenceUpdate = self._generateExternalReferenceUpdate(ctxt, tensorName, rectangles, tileIdxVar,

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