diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 42512e4fa..dc61b84e1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -554,4 +554,3 @@ jobs: compile-ara-${{ matrix.ara_config }} compile-apps-${{ matrix.ara_config }} compile-riscv-tests-${{ matrix.ara_config }} - benchmark-${{ matrix.ara_config }} diff --git a/hardware/Makefile b/hardware/Makefile index 927dd42f1..0100ac88f 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -158,6 +158,7 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi -Wno-UNSIGNED \ -Wno-WIDTH \ -Wno-WIDTHCONCAT \ + -Wno-SELRANGE \ --hierarchical \ tb/verilator/waiver.vlt \ --Mdir $(veril_library) \ diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 6773d5b82..ddf3b5765 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 6773d5b8278fca67268aad0cbffbfd141a39a42d +Subproject commit ddf3b576508f497c6bed63a282560fb7e66560e0 diff --git a/hardware/patches/0002-cva6-cache-size.patch b/hardware/patches/0002-cva6-cache-size.patch index 86331d7ee..591f7c8cb 100644 --- a/hardware/patches/0002-cva6-cache-size.patch +++ b/hardware/patches/0002-cva6-cache-size.patch @@ -1,5 +1,5 @@ diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv -index 78ab0bf..5a70ccd 100644 +index adc497e..f90c12e 100644 --- a/include/ariane_pkg.sv +++ b/include/ariane_pkg.sv @@ -457,14 +457,14 @@ package ariane_pkg; @@ -11,7 +11,7 @@ index 78ab0bf..5a70ccd 100644 localparam int unsigned ICACHE_SET_ASSOC = 4; // Must be between 4 to 64 localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); // in bit, contains also offset width localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN-ICACHE_INDEX_WIDTH; // in bit - localparam int unsigned ICACHE_LINE_WIDTH = 256; // in bit + localparam int unsigned ICACHE_LINE_WIDTH = 512; // in bit // D$ - localparam int unsigned CONFIG_L1D_SIZE = 32*1024; - localparam int unsigned DCACHE_SET_ASSOC = 8; // Must be between 4 to 64 diff --git a/hardware/src/ara_soc.sv b/hardware/src/ara_soc.sv index d2083cb0d..15783f23d 100644 --- a/hardware/src/ara_soc.sv +++ b/hardware/src/ara_soc.sv @@ -76,8 +76,12 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( // AXI // /////////// + // Peripheral AXI port data width + localparam AxiPeriphDataWidth = 64; + localparam AxiPeriphStrbWidth = AxiPeriphDataWidth / 8; + // Ariane's AXI port data width - localparam AxiNarrowDataWidth = 64; + localparam AxiNarrowDataWidth = ariane_pkg::DCACHE_LINE_WIDTH; localparam AxiNarrowStrbWidth = AxiNarrowDataWidth / 8; // Ara's AXI port data width localparam AxiWideDataWidth = AxiDataWidth; @@ -87,6 +91,8 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( localparam AxiCoreIdWidth = AxiSocIdWidth - 1; // Internal types + typedef logic [AxiPeriphDataWidth-1:0] axi_periph_data_t; + typedef logic [AxiPeriphStrbWidth-1:0] axi_periph_strb_t; typedef logic [AxiNarrowDataWidth-1:0] axi_narrow_data_t; typedef logic [AxiNarrowStrbWidth-1:0] axi_narrow_strb_t; typedef logic [AxiSocIdWidth-1:0] axi_soc_id_t; @@ -99,8 +105,10 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( axi_user_t) `AXI_TYPEDEF_ALL(soc_narrow, axi_addr_t, axi_soc_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) + `AXI_TYPEDEF_ALL(soc_periph, axi_addr_t, axi_soc_id_t, axi_periph_data_t, axi_periph_strb_t, + axi_user_t) `AXI_TYPEDEF_ALL(soc_wide, axi_addr_t, axi_soc_id_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_LITE_TYPEDEF_ALL(soc_narrow_lite, axi_addr_t, axi_narrow_data_t, axi_narrow_strb_t) + `AXI_LITE_TYPEDEF_ALL(soc_periph_lite, axi_addr_t, axi_periph_data_t, axi_periph_strb_t) // Buses system_req_t system_axi_req; @@ -108,8 +116,8 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( soc_wide_req_t [NrAXISlaves-1:0] periph_wide_axi_req; soc_wide_resp_t [NrAXISlaves-1:0] periph_wide_axi_resp; - soc_narrow_req_t [NrAXISlaves-1:0] periph_narrow_axi_req; - soc_narrow_resp_t [NrAXISlaves-1:0] periph_narrow_axi_resp; + soc_periph_req_t [NrAXISlaves-1:0] periph_narrow_axi_req; + soc_periph_resp_t [NrAXISlaves-1:0] periph_narrow_axi_resp; //////////////// // Crossbar // @@ -244,8 +252,8 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( axi2apb_64_32 #( .AXI4_ADDRESS_WIDTH(AxiAddrWidth ), - .AXI4_RDATA_WIDTH (AxiNarrowDataWidth), - .AXI4_WDATA_WIDTH (AxiNarrowDataWidth), + .AXI4_RDATA_WIDTH (AxiPeriphDataWidth), + .AXI4_WDATA_WIDTH (AxiPeriphDataWidth), .AXI4_ID_WIDTH (AxiSocIdWidth ), .AXI4_USER_WIDTH (AxiUserWidth ), .BUFF_DEPTH_SLAVE (2 ), @@ -310,19 +318,19 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( axi_dw_converter #( .AxiSlvPortDataWidth(AxiWideDataWidth ), - .AxiMstPortDataWidth(AxiNarrowDataWidth ), + .AxiMstPortDataWidth(AxiPeriphDataWidth ), .AxiAddrWidth (AxiAddrWidth ), .AxiIdWidth (AxiSocIdWidth ), .AxiMaxReads (2 ), .ar_chan_t (soc_wide_ar_chan_t ), - .mst_r_chan_t (soc_narrow_r_chan_t ), + .mst_r_chan_t (soc_periph_r_chan_t ), .slv_r_chan_t (soc_wide_r_chan_t ), - .aw_chan_t (soc_narrow_aw_chan_t ), + .aw_chan_t (soc_periph_aw_chan_t ), .b_chan_t (soc_wide_b_chan_t ), - .mst_w_chan_t (soc_narrow_w_chan_t ), + .mst_w_chan_t (soc_periph_w_chan_t ), .slv_w_chan_t (soc_wide_w_chan_t ), - .axi_mst_req_t (soc_narrow_req_t ), - .axi_mst_resp_t (soc_narrow_resp_t ), + .axi_mst_req_t (soc_periph_req_t ), + .axi_mst_resp_t (soc_periph_resp_t ), .axi_slv_req_t (soc_wide_req_t ), .axi_slv_resp_t (soc_wide_resp_t ) ) i_axi_slave_uart_dwc ( @@ -338,21 +346,21 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( // Control registers // ///////////////////////// - soc_narrow_lite_req_t axi_lite_ctrl_registers_req; - soc_narrow_lite_resp_t axi_lite_ctrl_registers_resp; + soc_periph_lite_req_t axi_lite_ctrl_registers_req; + soc_periph_lite_resp_t axi_lite_ctrl_registers_resp; axi_to_axi_lite #( .AxiAddrWidth (AxiAddrWidth ), - .AxiDataWidth (AxiNarrowDataWidth ), + .AxiDataWidth (AxiPeriphDataWidth ), .AxiIdWidth (AxiSocIdWidth ), .AxiUserWidth (AxiUserWidth ), .AxiMaxReadTxns (1 ), .AxiMaxWriteTxns(1 ), .FallThrough (1'b0 ), - .full_req_t (soc_narrow_req_t ), - .full_resp_t (soc_narrow_resp_t ), - .lite_req_t (soc_narrow_lite_req_t ), - .lite_resp_t (soc_narrow_lite_resp_t) + .full_req_t (soc_periph_req_t ), + .full_resp_t (soc_periph_resp_t ), + .lite_req_t (soc_periph_lite_req_t ), + .lite_resp_t (soc_periph_lite_resp_t) ) i_axi_to_axi_lite ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -366,10 +374,10 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( ctrl_registers #( .DRAMBaseAddr (DRAMBase ), .DRAMLength (DRAMLength ), - .DataWidth (AxiNarrowDataWidth ), + .DataWidth (AxiPeriphDataWidth ), .AddrWidth (AxiAddrWidth ), - .axi_lite_req_t (soc_narrow_lite_req_t ), - .axi_lite_resp_t(soc_narrow_lite_resp_t) + .axi_lite_req_t (soc_periph_lite_req_t ), + .axi_lite_resp_t(soc_periph_lite_resp_t) ) i_ctrl_registers ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -382,19 +390,19 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( axi_dw_converter #( .AxiSlvPortDataWidth(AxiWideDataWidth ), - .AxiMstPortDataWidth(AxiNarrowDataWidth ), + .AxiMstPortDataWidth(AxiPeriphDataWidth ), .AxiAddrWidth (AxiAddrWidth ), .AxiIdWidth (AxiSocIdWidth ), .AxiMaxReads (2 ), .ar_chan_t (soc_wide_ar_chan_t ), - .mst_r_chan_t (soc_narrow_r_chan_t ), + .mst_r_chan_t (soc_periph_r_chan_t ), .slv_r_chan_t (soc_wide_r_chan_t ), - .aw_chan_t (soc_narrow_aw_chan_t), - .b_chan_t (soc_narrow_b_chan_t ), - .mst_w_chan_t (soc_narrow_w_chan_t ), + .aw_chan_t (soc_periph_aw_chan_t), + .b_chan_t (soc_periph_b_chan_t ), + .mst_w_chan_t (soc_periph_w_chan_t ), .slv_w_chan_t (soc_wide_w_chan_t ), - .axi_mst_req_t (soc_narrow_req_t ), - .axi_mst_resp_t (soc_narrow_resp_t ), + .axi_mst_req_t (soc_periph_req_t ), + .axi_mst_resp_t (soc_periph_resp_t ), .axi_slv_req_t (soc_wide_req_t ), .axi_slv_resp_t (soc_wide_resp_t ) ) i_axi_slave_ctrl_dwc ( diff --git a/hardware/src/ara_system.sv b/hardware/src/ara_system.sv index a005c1d10..d9049ac9c 100644 --- a/hardware/src/ara_system.sv +++ b/hardware/src/ara_system.sv @@ -84,7 +84,16 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( logic inval_ready; ariane #( - .ArianeCfg(ArianeCfg) + .ArianeCfg (ArianeCfg ), + .AxiAddrWidth (AxiAddrWidth ), + .AxiDataWidth (AxiNarrowDataWidth ), + .AxiIdWidth (AxiIdWidth ), + .AxiUserWidth (ariane_axi::UserWidth), + .axi_ar_chan_t (ariane_axi_ar_t ), + .axi_aw_chan_t (ariane_axi_aw_t ), + .axi_w_chan_t (ariane_axi_w_t ), + .axi_req_t (ariane_axi_req_t ), + .axi_rsp_t (ariane_axi_resp_t ) ) i_ariane ( .clk_i (clk_i ), .rst_ni (rst_ni ),