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| 1 | +#!/bin/bash |
| 2 | +# Copyright (c) 2014-2018 ETH Zurich, University of Bologna |
| 3 | +# |
| 4 | +# Copyright and related rights are licensed under the Solderpad Hardware |
| 5 | +# License, Version 0.51 (the "License"); you may not use this file except in |
| 6 | +# compliance with the License. You may obtain a copy of the License at |
| 7 | +# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law |
| 8 | +# or agreed to in writing, software, hardware and materials distributed under |
| 9 | +# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR |
| 10 | +# CONDITIONS OF ANY KIND, either express or implied. See the License for the |
| 11 | +# specific language governing permissions and limitations under the License. |
| 12 | +# |
| 13 | +# Authors: |
| 14 | +# - Andreas Kurth <akurth@iis.ee.ethz.ch> |
| 15 | +# - Fabian Schuiki <fschuiki@iis.ee.ethz.ch> |
| 16 | +# - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch> |
| 17 | +# - Michael Rogenmoser <michaero@iis.ee.ethz.ch> |
| 18 | + |
| 19 | +set -euo pipefail |
| 20 | +ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) |
| 21 | + |
| 22 | +[ ! -z "$VERILATOR" ] || VERILATOR="verilator" |
| 23 | + |
| 24 | +SEEDS=(0) |
| 25 | + |
| 26 | +compile_and_run() { |
| 27 | + local tb_module="$1" |
| 28 | + shift |
| 29 | + local params=("$@") |
| 30 | + local build_dir="build_${tb_module}" |
| 31 | + |
| 32 | + # Build a unique directory name incorporating parameters to allow parallel runs |
| 33 | + for p in "${params[@]}"; do |
| 34 | + build_dir="${build_dir}_${p//=/_}" |
| 35 | + done |
| 36 | + |
| 37 | + mkdir -p "$build_dir" |
| 38 | + |
| 39 | + bender script verilator -t test -t rtl -t simulation > "$build_dir/verilator.f" |
| 40 | + |
| 41 | + VERILATOR_FLAGS=() |
| 42 | + VERILATOR_FLAGS+=(-Wno-fatal) |
| 43 | + VERILATOR_FLAGS+=(--timing) |
| 44 | + VERILATOR_FLAGS+=(--assert) |
| 45 | + VERILATOR_FLAGS+=(--binary) |
| 46 | + VERILATOR_FLAGS+=(--top-module "$tb_module") |
| 47 | + for p in "${params[@]}"; do |
| 48 | + VERILATOR_FLAGS+=("-G${p}") |
| 49 | + done |
| 50 | + VERILATOR_FLAGS+=(-f "$build_dir/verilator.f") |
| 51 | + VERILATOR_FLAGS+=(-Mdir "$build_dir/obj_dir") |
| 52 | + |
| 53 | + $VERILATOR "${VERILATOR_FLAGS[@]}" |
| 54 | + |
| 55 | + for seed in "${SEEDS[@]}"; do |
| 56 | + "$build_dir/obj_dir/V${tb_module}" "+verilator+seed+${seed}" |
| 57 | + done |
| 58 | +} |
| 59 | + |
| 60 | +exec_test() { |
| 61 | + if [ ! -e "$ROOT/test/tb_$1.sv" ]; then |
| 62 | + echo "Testbench for '$1' not found!" |
| 63 | + exit 1 |
| 64 | + fi |
| 65 | + case "$1" in |
| 66 | + axi_atop_filter) |
| 67 | + for MAX_TXNS in 1 3 12; do |
| 68 | + compile_and_run tb_axi_atop_filter \ |
| 69 | + "TB_N_TXNS=1000" \ |
| 70 | + "TB_AXI_MAX_WRITE_TXNS=${MAX_TXNS}" |
| 71 | + done |
| 72 | + ;; |
| 73 | + axi_cdc|axi_delayer) |
| 74 | + compile_and_run tb_$1 |
| 75 | + ;; |
| 76 | + axi_dw_downsizer) |
| 77 | + compile_and_run tb_axi_dw_downsizer \ |
| 78 | + "TbAxiSlvPortDataWidth=32" \ |
| 79 | + "TbAxiMstPortDataWidth=16" \ |
| 80 | + "TbInitialBStallCycles=100000" |
| 81 | + compile_and_run tb_axi_dw_downsizer \ |
| 82 | + "TbAxiSlvPortDataWidth=32" \ |
| 83 | + "TbAxiMstPortDataWidth=16" \ |
| 84 | + "TbInitialRStallCycles=100000" |
| 85 | + for AxiSlvPortDataWidth in 8 16 32 64 128 256 512 1024; do |
| 86 | + for (( AxiMstPortDataWidth = 8; \ |
| 87 | + AxiMstPortDataWidth < AxiSlvPortDataWidth; \ |
| 88 | + AxiMstPortDataWidth *= 2 )); \ |
| 89 | + do |
| 90 | + compile_and_run tb_axi_dw_downsizer \ |
| 91 | + "TbAxiSlvPortDataWidth=${AxiSlvPortDataWidth}" \ |
| 92 | + "TbAxiMstPortDataWidth=${AxiMstPortDataWidth}" |
| 93 | + done |
| 94 | + done |
| 95 | + ;; |
| 96 | + axi_dw_upsizer) |
| 97 | + for AxiSlvPortDataWidth in 8 16 32 64 128 256 512 1024; do |
| 98 | + for (( AxiMstPortDataWidth = AxiSlvPortDataWidth*2; \ |
| 99 | + AxiMstPortDataWidth <= 1024; \ |
| 100 | + AxiMstPortDataWidth *= 2 )); \ |
| 101 | + do |
| 102 | + compile_and_run tb_axi_dw_upsizer \ |
| 103 | + "TbAxiSlvPortDataWidth=${AxiSlvPortDataWidth}" \ |
| 104 | + "TbAxiMstPortDataWidth=${AxiMstPortDataWidth}" |
| 105 | + done |
| 106 | + done |
| 107 | + ;; |
| 108 | + axi_fifo) |
| 109 | + for DEPTH in 0 1 16; do |
| 110 | + for FALL_THROUGH in 0 1; do |
| 111 | + compile_and_run tb_axi_fifo \ |
| 112 | + "Depth=${DEPTH}" \ |
| 113 | + "FallThrough=${FALL_THROUGH}" |
| 114 | + done |
| 115 | + done |
| 116 | + ;; |
| 117 | + axi_iw_converter) |
| 118 | + for SLV_PORT_IW in 1 2 3 4 8; do |
| 119 | + MAX_SLV_PORT_IDS=$((2**SLV_PORT_IW)) |
| 120 | + MAX_UNIQ_SLV_PORT_IDS_OPTS=(1 2) |
| 121 | + EXCL_OPTS=(0) |
| 122 | + if [ $SLV_PORT_IW -eq 3 ]; then |
| 123 | + EXCL_OPTS+=(1) |
| 124 | + fi |
| 125 | + for EXCL in "${EXCL_OPTS[@]}"; do |
| 126 | + if [ $MAX_SLV_PORT_IDS -gt 2 ]; then |
| 127 | + MAX_UNIQ_SLV_PORT_IDS_OPTS+=(3 4) |
| 128 | + fi |
| 129 | + if [ $(($MAX_SLV_PORT_IDS/2)) -ge 4 ]; then |
| 130 | + MAX_UNIQ_SLV_PORT_IDS_OPTS+=($((MAX_SLV_PORT_IDS/2-1))) |
| 131 | + fi |
| 132 | + MAX_UNIQ_SLV_PORT_IDS_OPTS+=($MAX_SLV_PORT_IDS) |
| 133 | + for MST_PORT_IW in 1 2 3 4; do |
| 134 | + if [ $MST_PORT_IW -lt $SLV_PORT_IW ]; then |
| 135 | + for MAX_UNIQ_SLV_PORT_IDS in "${MAX_UNIQ_SLV_PORT_IDS_OPTS[@]}"; do |
| 136 | + MAX_MST_PORT_IDS=$((2**MST_PORT_IW)) |
| 137 | + if [ $MAX_UNIQ_SLV_PORT_IDS -le $MAX_MST_PORT_IDS ]; then |
| 138 | + compile_and_run tb_axi_iw_converter \ |
| 139 | + "TbEnExcl=${EXCL}" \ |
| 140 | + "TbAxiSlvPortIdWidth=${SLV_PORT_IW}" \ |
| 141 | + "TbAxiMstPortIdWidth=${MST_PORT_IW}" \ |
| 142 | + "TbAxiSlvPortMaxUniqIds=${MAX_UNIQ_SLV_PORT_IDS}" \ |
| 143 | + "TbAxiSlvPortMaxTxnsPerId=5" |
| 144 | + else |
| 145 | + compile_and_run tb_axi_iw_converter \ |
| 146 | + "TbEnExcl=${EXCL}" \ |
| 147 | + "TbAxiSlvPortIdWidth=${SLV_PORT_IW}" \ |
| 148 | + "TbAxiMstPortIdWidth=${MST_PORT_IW}" \ |
| 149 | + "TbAxiSlvPortMaxUniqIds=${MAX_UNIQ_SLV_PORT_IDS}" \ |
| 150 | + "TbAxiSlvPortMaxTxns=31" \ |
| 151 | + "TbAxiMstPortMaxUniqIds=$((2**MST_PORT_IW))" \ |
| 152 | + "TbAxiMstPortMaxTxnsPerId=7" |
| 153 | + fi |
| 154 | + done |
| 155 | + else |
| 156 | + compile_and_run tb_axi_iw_converter \ |
| 157 | + "TbEnExcl=${EXCL}" \ |
| 158 | + "TbAxiSlvPortIdWidth=${SLV_PORT_IW}" \ |
| 159 | + "TbAxiMstPortIdWidth=${MST_PORT_IW}" \ |
| 160 | + "TbAxiSlvPortMaxTxnsPerId=3" |
| 161 | + fi |
| 162 | + done |
| 163 | + done |
| 164 | + done |
| 165 | + ;; |
| 166 | + axi_lite_regs) |
| 167 | + SEEDS+=(10 42) |
| 168 | + for PRIV in 0 1; do |
| 169 | + for SECU in 0 1; do |
| 170 | + for BYTES in 42 200 369; do |
| 171 | + compile_and_run tb_axi_lite_regs \ |
| 172 | + "TbPrivProtOnly=${PRIV}" \ |
| 173 | + "TbSecuProtOnly=${SECU}" \ |
| 174 | + "TbRegNumBytes=${BYTES}" |
| 175 | + done |
| 176 | + done |
| 177 | + done |
| 178 | + ;; |
| 179 | + axi_lite_to_apb) |
| 180 | + for PIPE_REQ in 0 1; do |
| 181 | + for PIPE_RESP in 0 1; do |
| 182 | + compile_and_run tb_axi_lite_to_apb \ |
| 183 | + "TbPipelineRequest=${PIPE_REQ}" \ |
| 184 | + "TbPipelineResponse=${PIPE_RESP}" |
| 185 | + done |
| 186 | + done |
| 187 | + ;; |
| 188 | + axi_lite_to_axi) |
| 189 | + for DW in 8 16 32 64 128 256 512 1024; do |
| 190 | + compile_and_run tb_axi_lite_to_axi "TB_DW=${DW}" |
| 191 | + done |
| 192 | + ;; |
| 193 | + axi_sim_mem) |
| 194 | + for AW in 16 32 64; do |
| 195 | + for DW in 32 64 128 256 512 1024; do |
| 196 | + compile_and_run tb_axi_sim_mem \ |
| 197 | + "TbAddrWidth=${AW}" \ |
| 198 | + "TbDataWidth=${DW}" |
| 199 | + done |
| 200 | + done |
| 201 | + ;; |
| 202 | + axi_xbar) |
| 203 | + for NumMst in 1 6; do |
| 204 | + for NumSlv in 1 8; do |
| 205 | + for Atop in 0 1; do |
| 206 | + for Exclusive in 0 1; do |
| 207 | + for UniqueIds in 0 1; do |
| 208 | + compile_and_run tb_axi_xbar \ |
| 209 | + "TbNumMasters=${NumMst}" \ |
| 210 | + "TbNumSlaves=${NumSlv}" \ |
| 211 | + "TbEnAtop=${Atop}" \ |
| 212 | + "TbEnExcl=${Exclusive}" \ |
| 213 | + "TbUniqueIds=${UniqueIds}" |
| 214 | + done |
| 215 | + done |
| 216 | + done |
| 217 | + done |
| 218 | + done |
| 219 | + ;; |
| 220 | + axi_to_mem_banked) |
| 221 | + for MEM_LAT in 1 2; do |
| 222 | + for BANK_FACTOR in 1 2; do |
| 223 | + for NUM_BANKS in 1 2; do |
| 224 | + for AXI_DATA_WIDTH in 64 256; do |
| 225 | + ACT_BANKS=$((2*BANK_FACTOR*NUM_BANKS)) |
| 226 | + MEM_DATA_WIDTH=$((AXI_DATA_WIDTH/NUM_BANKS)) |
| 227 | + compile_and_run tb_axi_to_mem_banked \ |
| 228 | + "TbAxiDataWidth=${AXI_DATA_WIDTH}" \ |
| 229 | + "TbNumWords=2048" \ |
| 230 | + "TbNumBanks=${ACT_BANKS}" \ |
| 231 | + "TbMemDataWidth=${MEM_DATA_WIDTH}" \ |
| 232 | + "TbMemLatency=${MEM_LAT}" \ |
| 233 | + "TbNumWrites=2000" \ |
| 234 | + "TbNumReads=2000" |
| 235 | + done |
| 236 | + done |
| 237 | + done |
| 238 | + done |
| 239 | + ;; |
| 240 | + axi_lite_dw_converter) |
| 241 | + for DWSLV in 32 64 128; do |
| 242 | + for DWMST in 16 32 64; do |
| 243 | + compile_and_run tb_axi_lite_dw_converter \ |
| 244 | + "TbAxiDataWidthSlv=${DWSLV}" \ |
| 245 | + "TbAxiDataWidthMst=${DWMST}" |
| 246 | + done |
| 247 | + done |
| 248 | + ;; |
| 249 | + *) |
| 250 | + compile_and_run tb_$1 |
| 251 | + ;; |
| 252 | + esac |
| 253 | +} |
| 254 | + |
| 255 | +# Parse flags. |
| 256 | +PARAMS="" |
| 257 | +while (( "$#" )); do |
| 258 | + case "$1" in |
| 259 | + --random-seed) |
| 260 | + SEEDS+=(random) |
| 261 | + shift;; |
| 262 | + -*--*) # unsupported flag |
| 263 | + echo "Error: Unsupported flag '$1'." >&2 |
| 264 | + exit 1;; |
| 265 | + *) # preserve positional arguments |
| 266 | + PARAMS="$PARAMS $1" |
| 267 | + shift;; |
| 268 | + esac |
| 269 | +done |
| 270 | +eval set -- "$PARAMS" |
| 271 | + |
| 272 | +if [ "$#" -eq 0 ]; then |
| 273 | + tests=() |
| 274 | + while IFS= read -r -d $'\0'; do |
| 275 | + tb_name="$(basename -s .sv $REPLY)" |
| 276 | + dut_name="${tb_name#tb_}" |
| 277 | + tests+=("$dut_name") |
| 278 | + done < <(find "$ROOT/test" -name 'tb_*.sv' -a \( ! -name '*_pkg.sv' \) -print0) |
| 279 | +else |
| 280 | + tests=("$@") |
| 281 | +fi |
| 282 | + |
| 283 | +for t in "${tests[@]}"; do |
| 284 | + exec_test "$t" |
| 285 | +done |
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