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axi_demux_id_counters: Split to own module and add any_outstanding_trx_o port
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‎Bender.yml‎

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# Level 0
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- src/axi_pkg.sv
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# Level 1
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- src/axi_demux_id_counters.sv
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- src/axi_intf.sv
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# Level 2
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- src/axi_atop_filter.sv

‎src/axi_demux_id_counters.sv‎

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// Copyright (c) 2019 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Authors:
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// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
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// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>
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// - Thomas Benz <tbenz@iis.ee.ethz.ch>
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// - Andreas Kurth <akurth@iis.ee.ethz.ch>
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`include "common_cells/registers.svh"
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module axi_demux_id_counters #(
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// the lower bits of the AXI ID that should be considered, results in 2**AXI_ID_BITS counters
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parameter int unsigned AxiIdBits = 2,
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parameter int unsigned CounterWidth = 4,
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parameter type mst_port_select_t = logic
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// lookup
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input logic [AxiIdBits-1:0] lookup_axi_id_i,
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output mst_port_select_t lookup_mst_select_o,
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output logic lookup_mst_select_occupied_o,
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// push
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output logic full_o,
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input logic [AxiIdBits-1:0] push_axi_id_i,
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input mst_port_select_t push_mst_select_i,
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input logic push_i,
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// inject ATOPs in AR channel
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input logic [AxiIdBits-1:0] inject_axi_id_i,
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input logic inject_i,
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// pop
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input logic [AxiIdBits-1:0] pop_axi_id_i,
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input logic pop_i,
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// outstanding transactions
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output logic any_outstanding_trx_o
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);
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localparam int unsigned NoCounters = 2**AxiIdBits;
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typedef logic [CounterWidth-1:0] cnt_t;
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// registers, each gets loaded when push_en[i]
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mst_port_select_t [NoCounters-1:0] mst_select_q;
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// counter signals
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logic [NoCounters-1:0] push_en, inject_en, pop_en, occupied, cnt_full;
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//-----------------------------------
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// Lookup
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//-----------------------------------
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assign lookup_mst_select_o = mst_select_q[lookup_axi_id_i];
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assign lookup_mst_select_occupied_o = occupied[lookup_axi_id_i];
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//-----------------------------------
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// Push and Pop
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//-----------------------------------
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assign push_en = (push_i) ? (1 << push_axi_id_i) : '0;
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assign inject_en = (inject_i) ? (1 << inject_axi_id_i) : '0;
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assign pop_en = (pop_i) ? (1 << pop_axi_id_i) : '0;
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assign full_o = |cnt_full;
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//-----------------------------------
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// Status
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//-----------------------------------
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assign any_outstanding_trx_o = |occupied;
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// counters
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for (genvar i = 0; i < NoCounters; i++) begin : gen_counters
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logic cnt_en, cnt_down, overflow;
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cnt_t cnt_delta, in_flight;
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always_comb begin
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unique case ({push_en[i], inject_en[i], pop_en[i]})
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3'b001 : begin // pop_i = -1
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cnt_en = 1'b1;
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cnt_down = 1'b1;
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cnt_delta = cnt_t'(1);
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end
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3'b010 : begin // inject_i = +1
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cnt_en = 1'b1;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(1);
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end
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// 3'b011, inject_i & pop_i = 0 --> use default
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3'b100 : begin // push_i = +1
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cnt_en = 1'b1;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(1);
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end
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// 3'b101, push_i & pop_i = 0 --> use default
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3'b110 : begin // push_i & inject_i = +2
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cnt_en = 1'b1;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(2);
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end
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3'b111 : begin // push_i & inject_i & pop_i = +1
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cnt_en = 1'b1;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(1);
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end
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default : begin // do nothing to the counters
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cnt_en = 1'b0;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(0);
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end
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endcase
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end
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delta_counter #(
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.WIDTH ( CounterWidth ),
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.STICKY_OVERFLOW ( 1'b0 )
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) i_in_flight_cnt (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.clear_i ( 1'b0 ),
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.en_i ( cnt_en ),
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.load_i ( 1'b0 ),
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.down_i ( cnt_down ),
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.delta_i ( cnt_delta ),
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.d_i ( '0 ),
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.q_o ( in_flight ),
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.overflow_o ( overflow )
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);
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assign occupied[i] = |in_flight;
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assign cnt_full[i] = overflow | (&in_flight);
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// holds the selection signal for this id
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`FFLARN(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni)
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// pragma translate_off
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`ifndef VERILATOR
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`ifndef XSIM
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// Validate parameters.
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cnt_underflow: assert property(
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@(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else
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$fatal(1, "axi_demux_id_counters > Counter: %0d underflowed.\
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The reason is probably a faulty AXI response.", i);
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`endif
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`endif
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// pragma translate_on
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end
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endmodule
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‎src/axi_demux_simple.sv‎

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@@ -508,126 +508,3 @@ module axi_demux_simple #(
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// pragma translate_on
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end
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endmodule
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module axi_demux_id_counters #(
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// the lower bits of the AXI ID that should be considered, results in 2**AXI_ID_BITS counters
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parameter int unsigned AxiIdBits = 2,
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parameter int unsigned CounterWidth = 4,
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parameter type mst_port_select_t = logic
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// lookup
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input logic [AxiIdBits-1:0] lookup_axi_id_i,
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output mst_port_select_t lookup_mst_select_o,
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output logic lookup_mst_select_occupied_o,
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// push
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output logic full_o,
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input logic [AxiIdBits-1:0] push_axi_id_i,
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input mst_port_select_t push_mst_select_i,
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input logic push_i,
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// inject ATOPs in AR channel
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input logic [AxiIdBits-1:0] inject_axi_id_i,
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input logic inject_i,
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// pop
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input logic [AxiIdBits-1:0] pop_axi_id_i,
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input logic pop_i
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);
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localparam int unsigned NoCounters = 2**AxiIdBits;
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typedef logic [CounterWidth-1:0] cnt_t;
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// registers, each gets loaded when push_en[i]
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mst_port_select_t [NoCounters-1:0] mst_select_q;
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// counter signals
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logic [NoCounters-1:0] push_en, inject_en, pop_en, occupied, cnt_full;
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//-----------------------------------
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// Lookup
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//-----------------------------------
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assign lookup_mst_select_o = mst_select_q[lookup_axi_id_i];
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assign lookup_mst_select_occupied_o = occupied[lookup_axi_id_i];
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//-----------------------------------
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// Push and Pop
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//-----------------------------------
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assign push_en = (push_i) ? (1 << push_axi_id_i) : '0;
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assign inject_en = (inject_i) ? (1 << inject_axi_id_i) : '0;
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assign pop_en = (pop_i) ? (1 << pop_axi_id_i) : '0;
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assign full_o = |cnt_full;
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// counters
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for (genvar i = 0; i < NoCounters; i++) begin : gen_counters
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logic cnt_en, cnt_down, overflow;
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cnt_t cnt_delta, in_flight;
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always_comb begin
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unique case ({push_en[i], inject_en[i], pop_en[i]})
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3'b001 : begin // pop_i = -1
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cnt_en = 1'b1;
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cnt_down = 1'b1;
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cnt_delta = cnt_t'(1);
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end
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3'b010 : begin // inject_i = +1
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cnt_en = 1'b1;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(1);
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end
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// 3'b011, inject_i & pop_i = 0 --> use default
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3'b100 : begin // push_i = +1
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cnt_en = 1'b1;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(1);
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end
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// 3'b101, push_i & pop_i = 0 --> use default
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3'b110 : begin // push_i & inject_i = +2
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cnt_en = 1'b1;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(2);
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end
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3'b111 : begin // push_i & inject_i & pop_i = +1
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cnt_en = 1'b1;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(1);
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end
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default : begin // do nothing to the counters
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cnt_en = 1'b0;
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cnt_down = 1'b0;
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cnt_delta = cnt_t'(0);
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end
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endcase
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end
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delta_counter #(
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.WIDTH ( CounterWidth ),
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.STICKY_OVERFLOW ( 1'b0 )
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) i_in_flight_cnt (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.clear_i ( 1'b0 ),
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.en_i ( cnt_en ),
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.load_i ( 1'b0 ),
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.down_i ( cnt_down ),
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.delta_i ( cnt_delta ),
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.d_i ( '0 ),
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.q_o ( in_flight ),
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.overflow_o ( overflow )
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);
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assign occupied[i] = |in_flight;
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assign cnt_full[i] = overflow | (&in_flight);
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// holds the selection signal for this id
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`FFLARN(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni)
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// pragma translate_off
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`ifndef VERILATOR
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`ifndef XSIM
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// Validate parameters.
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cnt_underflow: assert property(
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@(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else
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$fatal(1, "axi_demux_id_counters > Counter: %0d underflowed.\
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The reason is probably a faulty AXI response.", i);
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`endif
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`endif
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// pragma translate_on
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end
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endmodule
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