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ezelioliezelioli
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Update time parameters to realtime type
1 parent 39f5f2d commit c6c494b

12 files changed

+54
-54
lines changed

‎src/axi_sim_mem.sv‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,9 @@ module axi_sim_mem #(
4646
/// Clear error on access
4747
parameter bit ClearErrOnAccess = 1'b0,
4848
/// Application delay (measured after rising clock edge)
49-
parameter time ApplDelay = 0ps,
49+
parameter realtime ApplDelay = 0ps,
5050
/// Acquisition delay (measured after rising clock edge)
51-
parameter time AcqDelay = 0ps
51+
parameter realtime AcqDelay = 0ps
5252
) (
5353
/// Rising-edge clock
5454
input logic clk_i,
@@ -361,8 +361,8 @@ module axi_sim_mem_intf #(
361361
parameter bit WARN_UNINITIALIZED = 1'b0,
362362
parameter UNINITIALIZED_DATA = "undefined",
363363
parameter bit ClearErrOnAccess = 1'b0,
364-
parameter time APPL_DELAY = 0ps,
365-
parameter time ACQ_DELAY = 0ps
364+
parameter realtime APPL_DELAY = 0ps,
365+
parameter realtime ACQ_DELAY = 0ps
366366
) (
367367
input logic clk_i,
368368
input logic rst_ni,
@@ -443,8 +443,8 @@ module axi_sim_mem_multiport_intf #(
443443
parameter bit WARN_UNINITIALIZED = 1'b0,
444444
parameter UNINITIALIZED_DATA = "undefined",
445445
parameter bit ClearErrOnAccess = 1'b0,
446-
parameter time APPL_DELAY = 0ps,
447-
parameter time ACQ_DELAY = 0ps
446+
parameter realtime APPL_DELAY = 0ps,
447+
parameter realtime ACQ_DELAY = 0ps
448448
) (
449449
input logic clk_i,
450450
input logic rst_ni,

‎src/axi_test.sv‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,8 @@ package axi_test;
2626
class axi_lite_driver #(
2727
parameter int AW = 32 ,
2828
parameter int DW = 32 ,
29-
parameter time TA = 0ns , // stimuli application time
30-
parameter time TT = 0ns // stimuli test time
29+
parameter realtime TA = 0ns , // stimuli application time
30+
parameter realtime TT = 0ns // stimuli test time
3131
);
3232
virtual AXI_LITE_DV #(
3333
.AXI_ADDR_WIDTH(AW),
@@ -285,8 +285,8 @@ package axi_test;
285285
parameter int unsigned DW = 32 ,
286286
parameter int unsigned IW = 8 ,
287287
parameter int unsigned UW = 1 ,
288-
parameter time TA = 0ns , // stimuli application time
289-
parameter time TT = 0ns // stimuli test time
288+
parameter realtime TA = 0ns , // stimuli application time
289+
parameter realtime TT = 0ns // stimuli test time
290290
);
291291
virtual AXI_BUS_DV #(
292292
.AXI_ADDR_WIDTH(AW),
@@ -686,8 +686,8 @@ package axi_test;
686686
parameter int IW = 8,
687687
parameter int UW = 1,
688688
// Stimuli application and test time
689-
parameter time TA = 0ps,
690-
parameter time TT = 0ps,
689+
parameter realtime TA = 0ps,
690+
parameter realtime TT = 0ps,
691691
// Maximum number of read and write transactions in flight
692692
parameter int MAX_READ_TXNS = 1,
693693
parameter int MAX_WRITE_TXNS = 1,
@@ -1297,8 +1297,8 @@ package axi_test;
12971297
parameter int IW = 8,
12981298
parameter int UW = 1,
12991299
// Stimuli application and test time
1300-
parameter time TA = 0ps,
1301-
parameter time TT = 0ps,
1300+
parameter realtime TA = 0ps,
1301+
parameter realtime TT = 0ps,
13021302
parameter bit RAND_RESP = 0,
13031303
// Upper and lower bounds on wait cycles on Ax, W, and resp (R and B) channels
13041304
parameter int AX_MIN_WAIT_CYCLES = 0,
@@ -1528,8 +1528,8 @@ package axi_test;
15281528
parameter int unsigned AW = 0,
15291529
parameter int unsigned DW = 0,
15301530
// Stimuli application and test time
1531-
parameter time TA = 2ns,
1532-
parameter time TT = 8ns,
1531+
parameter realtime TA = 2ns,
1532+
parameter realtime TT = 8ns,
15331533
parameter int unsigned MIN_ADDR = 32'h0000_0000,
15341534
parameter int unsigned MAX_ADDR = 32'h1000_0000,
15351535
// Maximum number of open transactions
@@ -1697,8 +1697,8 @@ package axi_test;
16971697
parameter int unsigned AW = 0,
16981698
parameter int unsigned DW = 0,
16991699
// Stimuli application and test time
1700-
parameter time TA = 2ns,
1701-
parameter time TT = 8ns,
1700+
parameter realtime TA = 2ns,
1701+
parameter realtime TT = 8ns,
17021702
// Upper and lower bounds on wait cycles on Ax, W, and resp (R and B) channels
17031703
parameter int AX_MIN_WAIT_CYCLES = 0,
17041704
parameter int AX_MAX_WAIT_CYCLES = 100,
@@ -1835,7 +1835,7 @@ package axi_test;
18351835
/// AXI4+ATOP user width
18361836
parameter int unsigned UW = 0,
18371837
/// Stimuli test time
1838-
parameter time TT = 0ns
1838+
parameter realtime TT = 0ns
18391839
);
18401840

18411841
typedef axi_test::axi_driver #(
@@ -1930,7 +1930,7 @@ package axi_test;
19301930
/// AXI4+ATOP user width
19311931
parameter int unsigned UW = 0,
19321932
/// Stimuli test time
1933-
parameter time TT = 0ns
1933+
parameter realtime TT = 0ns
19341934
);
19351935
// Number of checks
19361936
localparam int unsigned NUM_CHECKS = 32'd3;
@@ -2353,8 +2353,8 @@ package axi_test;
23532353
parameter int IW = 8,
23542354
parameter int UW = 1,
23552355
// Stimuli application and test time
2356-
parameter time TA = 0ps,
2357-
parameter time TT = 0ps
2356+
parameter realtime TA = 0ps,
2357+
parameter realtime TT = 0ps
23582358
);
23592359

23602360
typedef axi_test::axi_driver #(
@@ -2579,7 +2579,7 @@ endpackage
25792579
// a log file per id for the reads
25802580
// atomic transactions with read response are injected into the corresponding log file of the read
25812581
module axi_chan_logger #(
2582-
parameter time TestTime = 8ns, // Time after clock, where sampling happens
2582+
parameter realtime TestTime = 8ns, // Time after clock, where sampling happens
25832583
parameter string LoggerName = "axi_logger", // name of the logger
25842584
parameter type aw_chan_t = logic, // axi AW type
25852585
parameter type w_chan_t = logic, // axi W type

‎test/tb_axi_atop_filter.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,9 @@ module tb_axi_atop_filter #(
2424
parameter int unsigned TB_AXI_MAX_READ_TXNS = 10,
2525
parameter int unsigned TB_AXI_MAX_WRITE_TXNS = 12,
2626
// TB Parameters
27-
parameter time TB_TCLK = 10ns,
28-
parameter time TB_TA = TB_TCLK * 1/4,
29-
parameter time TB_TT = TB_TCLK * 3/4,
27+
parameter realtime TB_TCLK = 10ns,
28+
parameter realtime TB_TA = TB_TCLK * 1/4,
29+
parameter realtime TB_TT = TB_TCLK * 3/4,
3030
parameter int unsigned TB_REQ_MIN_WAIT_CYCLES = 0,
3131
parameter int unsigned TB_REQ_MAX_WAIT_CYCLES = 10,
3232
parameter int unsigned TB_RESP_MIN_WAIT_CYCLES = 0,

‎test/tb_axi_bus_compare.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,15 @@
1010
/// Testbench for `axi_bus_compare`
1111
module tb_axi_bus_compare #(
1212
// TB Parameters
13-
parameter time TbTclk = 10ns,
13+
parameter realtime TbTclk = 10ns,
1414
// Module Parameters
1515
parameter int unsigned TbAddrWidth = 32'd64,
1616
parameter int unsigned TbDataWidth = 32'd128,
1717
parameter int unsigned TbIdWidth = 32'd6,
1818
parameter int unsigned TbUserWidth = 32'd2,
1919
parameter bit TbWarnUninitialized = 1'b0,
20-
parameter time TbApplDelay = 2ns,
21-
parameter time TbAcqDelay = 8ns
20+
parameter realtime TbApplDelay = 2ns,
21+
parameter realtime TbAcqDelay = 8ns
2222
);
2323

2424
logic clk,

‎test/tb_axi_cdc.sv‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -24,12 +24,12 @@ module tb_axi_cdc #(
2424
parameter int unsigned AXI_MAX_READ_TXNS = 10,
2525
parameter int unsigned AXI_MAX_WRITE_TXNS = 12,
2626
// TB Parameters
27-
parameter time TCLK_UPSTREAM = 10ns,
28-
parameter time TA_UPSTREAM = TCLK_UPSTREAM * 1/4,
29-
parameter time TT_UPSTREAM = TCLK_UPSTREAM * 3/4,
30-
parameter time TCLK_DOWNSTREAM = 3ns,
31-
parameter time TA_DOWNSTREAM = TCLK_DOWNSTREAM * 1/4,
32-
parameter time TT_DOWNSTREAM = TCLK_DOWNSTREAM * 3/4,
27+
parameter realtime TCLK_UPSTREAM = 10ns,
28+
parameter realtime TA_UPSTREAM = TCLK_UPSTREAM * 1/4,
29+
parameter realtime TT_UPSTREAM = TCLK_UPSTREAM * 3/4,
30+
parameter realtime TCLK_DOWNSTREAM = 3ns,
31+
parameter realtime TA_DOWNSTREAM = TCLK_DOWNSTREAM * 1/4,
32+
parameter realtime TT_DOWNSTREAM = TCLK_DOWNSTREAM * 3/4,
3333
parameter int unsigned REQ_MIN_WAIT_CYCLES = 0,
3434
parameter int unsigned REQ_MAX_WAIT_CYCLES = 10,
3535
parameter int unsigned RESP_MIN_WAIT_CYCLES = 0,

‎test/tb_axi_dw_downsizer.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,9 @@ module tb_axi_dw_downsizer #(
2424
parameter int unsigned TbInitialBStallCycles = 0,
2525
parameter int unsigned TbInitialRStallCycles = 0,
2626
// TB Parameters
27-
parameter time TbCyclTime = 10ns,
28-
parameter time TbApplTime = 2ns ,
29-
parameter time TbTestTime = 8ns
27+
parameter realtime TbCyclTime = 10ns,
28+
parameter realtime TbApplTime = 2ns ,
29+
parameter realtime TbTestTime = 8ns
3030
);
3131

3232
/*********************

‎test/tb_axi_dw_pkg.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ package tb_axi_dw_pkg ;
3434
parameter int unsigned AxiIdWidth ,
3535
parameter int unsigned AxiUserWidth ,
3636
// Stimuli application and test time
37-
parameter time TimeTest
37+
parameter realtime TimeTest
3838
);
3939

4040
localparam AxiSlvPortStrbWidth = AxiSlvPortDataWidth / 8;
@@ -577,7 +577,7 @@ package tb_axi_dw_pkg ;
577577
parameter int unsigned AxiIdWidth ,
578578
parameter int unsigned AxiUserWidth ,
579579
// Stimuli application and test time
580-
parameter time TimeTest
580+
parameter realtime TimeTest
581581
) extends axi_dw_monitor #(
582582
.AxiAddrWidth (AxiAddrWidth ),
583583
.AxiSlvPortDataWidth(AxiSlvPortDataWidth),
@@ -909,7 +909,7 @@ package tb_axi_dw_pkg ;
909909
parameter int unsigned AxiIdWidth ,
910910
parameter int unsigned AxiUserWidth ,
911911
// Stimuli application and test time
912-
parameter time TimeTest
912+
parameter realtime TimeTest
913913
) extends axi_dw_monitor #(
914914
.AxiAddrWidth (AxiAddrWidth ),
915915
.AxiSlvPortDataWidth(AxiSlvPortDataWidth),

‎test/tb_axi_dw_upsizer.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@ module tb_axi_dw_upsizer #(
2222
parameter int unsigned TbAxiMstPortDataWidth = 64 ,
2323
parameter int unsigned TbAxiUserWidth = 8 ,
2424
// TB Parameters
25-
parameter time TbCyclTime = 10ns,
26-
parameter time TbApplTime = 2ns ,
27-
parameter time TbTestTime = 8ns
25+
parameter realtime TbCyclTime = 10ns,
26+
parameter realtime TbApplTime = 2ns ,
27+
parameter realtime TbTestTime = 8ns
2828
);
2929

3030
/*********************

‎test/tb_axi_modify_address.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,9 @@ module tb_axi_modify_address #(
2323
parameter int unsigned AXI_ID_WIDTH = 3,
2424
parameter int unsigned AXI_USER_WIDTH = 2,
2525
// TB Parameters
26-
parameter time TCLK = 10ns,
27-
parameter time TA = TCLK * 1/4,
28-
parameter time TT = TCLK * 3/4,
26+
parameter realtime TCLK = 10ns,
27+
parameter realtime TA = TCLK * 1/4,
28+
parameter realtime TT = TCLK * 3/4,
2929
parameter int unsigned REQ_MIN_WAIT_CYCLES = 0,
3030
parameter int unsigned REQ_MAX_WAIT_CYCLES = 10,
3131
parameter int unsigned RESP_MIN_WAIT_CYCLES = 0,

‎test/tb_axi_sim_mem.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,15 @@
1111
/// Testbench for `axi_sim_mem`
1212
module tb_axi_sim_mem #(
1313
// TB Parameters
14-
parameter time TbTclk = 10ns,
14+
parameter realtime TbTclk = 10ns,
1515
// Module Parameters
1616
parameter int unsigned TbAddrWidth = 32'd64,
1717
parameter int unsigned TbDataWidth = 32'd128,
1818
parameter int unsigned TbIdWidth = 32'd6,
1919
parameter int unsigned TbUserWidth = 32'd2,
2020
parameter bit TbWarnUninitialized = 1'b0,
21-
parameter time TbApplDelay = 2ns,
22-
parameter time TbAcqDelay = 8ns
21+
parameter realtime TbApplDelay = 2ns,
22+
parameter realtime TbAcqDelay = 8ns
2323
);
2424

2525
logic clk,

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