Add axi_fifo_delay_dyn to delay AXI signals

Author: thommythomaso

Bender.yml

@@ -47,6 +47,7 @@ sources:
   - src/axi_dw_downsizer.sv
   - src/axi_dw_upsizer.sv
   - src/axi_fifo.sv
+  - src/axi_fifo_delay_dyn.sv
   - src/axi_id_remap.sv
   - src/axi_id_prepend.sv
   - src/axi_isolate.sv

README.md

@@ -80,8 +80,10 @@ The following modules are meant to be used for verification purposes only but ar
 | Name                                                 | Description                                                                                             |
 |------------------------------------------------------|---------------------------------------------------------------------------------------------------------|
 | [`axi_bus_compare`](src/axi_bus_compare.sv)          | Compares two buses of the same type (and in the same clock domain), returns events on mismatch.         |
+| [`axi_fifo_delay_dyn`](src/axi_fifo_delay_dyn.sv)    | Delay and buffer each channel of an AXI bus individually.                                               |
 | [`axi_slave_compare`](src/axi_slave_compare.sv)      | Compares two slave devices of the same type (and in the same clock domain), returns events on mismatch. |
 
+
 ### Simulation-Only Modules
 
 In addition to the modules above, which are available in synthesis and simulation, the following modules are available only in simulation.  Those modules are widely used in our testbenches, but they are also suitable to build testbenches for AXI modules and systems outside this repository.

axi.core

@@ -27,6 +27,7 @@ filesets:
       - src/axi_dw_downsizer.sv
       - src/axi_dw_upsizer.sv
       - src/axi_fifo.sv
+      - src/axi_fifo_delay_dyn.sv
       - src/axi_id_remap.sv
       - src/axi_id_prepend.sv
       - src/axi_isolate.sv