combinatorial loop in `axi_to_mem`

[0BAB1]

I get the following error when trying to write a bitstream in vivado with the axi_to_mem module in the design.

[DRC LUTLP-1] Combinatorial Loop Alert: 9 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_mem_to_banks/gen_resp_regs[0].i_ft_reg/fifo_i/gen_buf.cnt_q_reg[1]. Please evaluate your design. The cells in the loop are: design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_meta_buf/fifo_i/gen_oup_state[0].oup_state_q_i_3, design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_sel_buf/fifo_i/inp_state_q_i_2__0, design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_meta_buf/fifo_i/inp_state_q_i_3, design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_sel_buf/fifo_i/inp_state_q_i_4, design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_mem_to_banks/gen_resp_regs[0].i_ft_reg/fifo_i/mem_q[0][addr][11]_i_1, design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_sel_buf/fifo_i/mem_q[0][addr][11]_i_4, design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_mem_to_banks/gen_resp_regs[0].i_ft_reg/fifo_i/mem_q[0][addr][11]_i_5, design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_sel_buf/fifo_i/status_cnt_q[1]_i_3__0, and design_1_i/top_0/inst/wrapped/debug_mem_conv/i_axi_to_mem/i_axi_to_detailed_mem/i_sel_buf/fifo_i/status_cnt_q[1]_i_4.

Is this expected behavior ? It does not look like my own design is mentionned in the looping logic so I wonder if I can just add the bypassing constraint and expect it to work.

Best