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Hi,
I have a design with two (relevant) clocks, CLK100 and CLK200 and they are synchronous., I need to connect a master on the CLK100 domain to a slave on the CLK200 domain.
Reviewing the available modules from the AXI library there does not appear to be a syncronous bridge to perform the clock conversion between the bus segments.
But there is the AXI_CDC module, I have two questions:
- Would the AXI_CDC module be suitable to connect a CLK100 master to a CLK200 slave without applying any async contraints (given the two clocks in my case are synchronous)?
- Does the AXI_CDC design rely on the two clock domains being truly asynchronous? ie Would using two clock that are synchronous be an issue? (with or without async contraints)
Cheers,
Roo
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