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registers.svh: Merge explicit and implicit macros (#117)
Merged explicit and implicit macros into `` `FF `` and `` `FFL `` for asynchronous FFs without and with load-enable, respectively. The old macros `` `FFARN `` and `` `FFLARN `` are retained for compatibility but a deprecation notice was added to them.
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‎CHANGELOG.md‎

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@@ -5,6 +5,8 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
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and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
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## Unreleased
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### Changed
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- `registers.svh`: Merge explicit and implicit register variants into `` `FF `` and `` `FFL `` macros
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## 1.21.0 - 2021-01-28
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### Changed

‎README.md‎

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@@ -114,21 +114,21 @@ The header file `registers.svh` contains macros that expand to descriptions of r
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To avoid misuse of `always_ff` blocks, only the following macros shall be used to describe sequential behavior.
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The use of linter rules that flag explicit uses of `always_ff` in source code is encouraged.
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| Macro | Arguments | Description |
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| ------------ | --------------------------------------------------------------- | ----------------------------------------------------------------------- |
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| `` `FF`` | `q_sig`, `d_sig`, `rst_val` | Flip-flop with asynchronous active-low reset (implicit) |
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| `` `FFAR`` | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `arst_sig` | Flip-flop with asynchronous active-high reset |
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| `` `FFARN`` | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `arstn_sig` | Flip-flop with asynchronous active-low reset |
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| `` `FFSR`` | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `rst_sig` | Flip-flop with synchronous active-high reset |
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| `` `FFSRN`` | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `rstn_sig` | Flip-flop with synchronous active-low reset |
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| `` `FFNR`` | `q_sig`, `d_sig`, `clk_sig` | Flip-flop without reset |
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| | | |
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| `` `FFL`` | `q_sig`, `d_sig`, `load_ena`, `rst_val` | Flip-flop with load-enable and asynchronous active-low reset (implicit) |
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| `` `FFLAR`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `arst_sig` | Flip-flop with load-enable and asynchronous active-high reset |
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| `` `FFLARN`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `arstn_sig` | Flip-flop with load-enable and asynchronous active-low reset |
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| `` `FFLSR`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `rst_sig` | Flip-flop with load-enable and synchronous active-high reset |
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| `` `FFLSRN`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `rstn_sig` | Flip-flop with load-enable and synchronous active-low reset |
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| `` `FFLNR`` | `q_sig`, `d_sig`, `load_ena`, `clk_sig` | Flip-flop with load-enable without reset |
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| Macro | Arguments | Description |
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| ------------ | ----------------------------------------------------------------- | ------------------------------------------------------------------------- |
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| `` `FF`` | `q_sig`, `d_sig`, `rst_val`, (`clk_sig`, `arstn_sig`) | Flip-flop with asynchronous active-low reset |
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| `` `FFAR`` | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `arst_sig` | Flip-flop with asynchronous active-high reset |
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| `` `FFARN`` | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `arstn_sig` | *deprecated* Flip-flop with asynchronous active-low reset |
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| `` `FFSR`` | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `rst_sig` | Flip-flop with synchronous active-high reset |
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| `` `FFSRN`` | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `rstn_sig` | Flip-flop with synchronous active-low reset |
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| `` `FFNR`` | `q_sig`, `d_sig`, `clk_sig` | Flip-flop without reset |
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| | | |
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| `` `FFL`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, (`clk_sig`, `arstn_sig`) | Flip-flop with load-enable and asynchronous active-low reset |
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| `` `FFLAR`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `arst_sig` | Flip-flop with load-enable and asynchronous active-high reset |
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| `` `FFLARN`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `arstn_sig` | *deprecated* Flip-flop with load-enable and asynchronous active-low reset |
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| `` `FFLSR`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `rst_sig` | Flip-flop with load-enable and synchronous active-high reset |
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| `` `FFLSRN`` | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `rstn_sig` | Flip-flop with load-enable and synchronous active-low reset |
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| `` `FFLNR`` | `q_sig`, `d_sig`, `load_ena`, `clk_sig` | Flip-flop with load-enable without reset |
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- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
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- *Argument suffix `_sig` indicates signal names for present and next state as well as clocks and resets.*
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- *Argument `rst_val` specifies the value literal to be assigned upon reset.*

‎include/common_cells/registers.svh‎

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@@ -1,4 +1,4 @@
1-
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright 2018, 2021 ETH Zurich and University of Bologna.
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//
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// SPDX-License-Identifier: SHL-0.51
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//
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// Author: Stefan Mach <[email protected]>
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// Description: Common register defines for RTL designs
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// Common register defines for RTL designs
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`ifndef COMMON_CELLS_REGISTERS_SVH_
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`define COMMON_CELLS_REGISTERS_SVH_
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// Abridged Summary of available FF macros:
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// `FF: asynchronous active-low reset (implicit clock and reset)
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// `FF: asynchronous active-low reset
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// `FFAR: asynchronous active-high reset
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// `FFARN: asynchronous active-low reset
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// `FFARN: [deprecated] asynchronous active-low reset
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// `FFSR: synchronous active-high reset
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// `FFSRN: synchronous active-low reset
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// `FFNR: without reset
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// `FFL: load-enable and asynchronous active-low reset (implicit clock and reset)
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// `FFL: load-enable and asynchronous active-low reset
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// `FFLAR: load-enable and asynchronous active-high reset
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// `FFLARN: load-enable and asynchronous active-low reset
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// `FFLARN: [deprecated] load-enable and asynchronous active-low reset
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// `FFLARNC: load-enable and asynchronous active-low reset and synchronous active-high clear
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// `FFLSR: load-enable and synchronous active-high reset
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// `FFLSRN: load-enable and synchronous active-low reset
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// `FFLNR: load-enable without reset
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`define REG_DFLT_CLK clk_i
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`define REG_DFLT_RST rst_ni
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// Flip-Flop with asynchronous active-low reset (implicit clock and reset)
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// Flip-Flop with asynchronous active-low reset
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// __q: Q output of FF
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// __d: D input of FF
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// __reset_value: value assigned upon reset
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// Implicit:
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// clk_i: clock input
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// rst_ni: reset input (asynchronous, active low)
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`define FF(__q, __d, __reset_value) \
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always_ff @(posedge clk_i or negedge rst_ni) begin \
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if (!rst_ni) begin \
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__q <= (__reset_value); \
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end else begin \
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__q <= (__d); \
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end \
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// (__clk: clock input)
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// (__arst_n: asynchronous reset, active-low)
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`define FF(__q, __d, __reset_value, __clk = `REG_DFLT_CLK, __arst_n = `REG_DFLT_RST) \
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always_ff @(posedge (__clk) or negedge (__arst_n)) begin \
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if (!__arst_n) begin \
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__q <= (__reset_value); \
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end else begin \
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__q <= (__d); \
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end \
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end
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// Flip-Flop with asynchronous active-high reset
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// __q: Q output of FF
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// __d: D input of FF
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// __reset_value: value assigned upon reset
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// __clk: clock input
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// __arst: asynchronous reset
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// __arst: asynchronous reset, active-high
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`define FFAR(__q, __d, __reset_value, __clk, __arst) \
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always_ff @(posedge (__clk) or posedge (__arst)) begin \
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if (__arst) begin \
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end \
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end
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// DEPRECATED - use `FF instead
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// Flip-Flop with asynchronous active-low reset
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// __q: Q output of FF
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// __d: D input of FF
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// __reset_value: value assigned upon reset
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// __clk: clock input
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// __arst_n: asynchronous reset
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`define FFARN(__q, __d, __reset_value, __clk, __arst_n) \
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always_ff @(posedge (__clk) or negedge (__arst_n)) begin \
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if (!__arst_n) begin \
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__q <= (__reset_value); \
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end else begin \
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__q <= (__d); \
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end \
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end
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// __arst_n: asynchronous reset, active-low
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`define FFARN(__q, __d, __reset_value, __clk, __arst_n) \
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`FF(__q, __d, __reset_value, __clk, __arst_n)
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// Flip-Flop with synchronous active-high reset
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// __q: Q output of FF
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// __d: D input of FF
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// __reset_value: value assigned upon reset
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// __clk: clock input
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// __reset_clk: reset input
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// __reset_clk: reset input, active-high
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`define FFSR(__q, __d, __reset_value, __clk, __reset_clk) \
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`ifndef VERILATOR \
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/``* synopsys sync_set_reset `"__reset_clk`" *``/ \
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// __d: D input of FF
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// __reset_value: value assigned upon reset
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// __clk: clock input
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// __reset_n_clk: reset input
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// __reset_n_clk: reset input, active-low
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`define FFSRN(__q, __d, __reset_value, __clk, __reset_n_clk) \
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`ifndef VERILATOR \
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/``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \
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// __d: D input of FF
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// __load: load d value into FF
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// __reset_value: value assigned upon reset
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// Implicit:
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// clk_i: clock input
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// rst_ni: reset input (asynchronous, active low)
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`define FFL(__q, __d, __load, __reset_value) \
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always_ff @(posedge clk_i or negedge rst_ni) begin \
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if (!rst_ni) begin \
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__q <= (__reset_value); \
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end else begin \
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__q <= (__load) ? (__d) : (__q); \
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end \
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// (__clk: clock input)
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// (__arst_n: asynchronous reset, active-low)
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`define FFL(__q, __d, __load, __reset_value, __clk = `REG_DFLT_CLK, __arst_n = `REG_DFLT_RST) \
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always_ff @(posedge (__clk) or negedge (__arst_n)) begin \
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if (!__arst_n) begin \
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__q <= (__reset_value); \
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end else begin \
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__q <= (__load) ? (__d) : (__q); \
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end \
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end
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// Flip-Flop with load-enable and asynchronous active-high reset
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// __load: load d value into FF
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// __reset_value: value assigned upon reset
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// __clk: clock input
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// __arst: asynchronous reset
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// __arst: asynchronous reset, active-high
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`define FFLAR(__q, __d, __load, __reset_value, __clk, __arst) \
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always_ff @(posedge (__clk) or posedge (__arst)) begin \
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if (__arst) begin \
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145143
end \
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end
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// DEPRECATED - use `FFL instead
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// Flip-Flop with load-enable and asynchronous active-low reset
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// __q: Q output of FF
150149
// __d: D input of FF
151150
// __load: load d value into FF
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// __reset_value: value assigned upon reset
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// __clk: clock input
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// __arst_n: asynchronous reset
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// __arst_n: asynchronous reset, active-low
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`define FFLARN(__q, __d, __load, __reset_value, __clk, __arst_n) \
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always_ff @(posedge (__clk) or negedge (__arst_n)) begin \
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if (!__arst_n) begin \
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__q <= (__reset_value); \
159-
end else begin \
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__q <= (__load) ? (__d) : (__q); \
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end \
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end
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`FFL(__q, __d, __load, __reset_value, __clk, __arst_n)
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164157
// Flip-Flop with load-enable and synchronous active-high reset
165158
// __q: Q output of FF
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// __d: D input of FF
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// __load: load d value into FF
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// __reset_value: value assigned upon reset
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// __clk: clock input
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// __reset_clk: reset input
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// __reset_clk: reset input, active-high
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`define FFLSR(__q, __d, __load, __reset_value, __clk, __reset_clk) \
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`ifndef VERILATOR \
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/``* synopsys sync_set_reset `"__reset_clk`" *``/ \
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// __load: load d value into FF
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// __reset_value: value assigned upon reset
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// __clk: clock input
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// __reset_n_clk: reset input
178+
// __reset_n_clk: reset input, active-low
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`define FFLSRN(__q, __d, __load, __reset_value, __clk, __reset_n_clk) \
187180
`ifndef VERILATOR \
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/``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \
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198191
// __clear: assign reset value into FF
199192
// __reset_value: value assigned upon reset
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// __clk: clock input
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// __arst_n: asynchronous reset
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// __arst_n: asynchronous reset, active-low
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`define FFLARNC(__q, __d, __load, __clear, __reset_value, __clk, __arst_n) \
203196
`ifndef VERILATOR \
204197
/``* synopsys sync_set_reset `"__clear`" *``/ \

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