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[HW]: Add mem_multibanked_pwrgate for correct power management
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‎Bender.yml‎

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- src/lfsr_8bit.sv
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- src/lossy_valid_to_stream.sv
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- src/mv_filter.sv
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- src/mem_multibank_pwrgate.sv
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- src/onehot_to_bin.sv
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- src/plru_tree.sv
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- src/passthrough_stream_fifo.sv
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- test/fifo_tb.sv
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- test/graycode_tb.sv
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- test/id_queue_tb.sv
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- test/mem_multibank_pwrgate_tb.sv
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- test/passthrough_stream_fifo_tb.sv
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- test/popcount_tb.sv
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- test/rr_arb_tree_tb.sv

‎src/mem_multibank_pwrgate.sv‎

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// Copyright 2024 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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//
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// Lorenzo Leone <[email protected]>
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// ## Description:
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// A wrapper for `tc_sram_impl` that instantiates logic banks with retention mode
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// or power-off capability.
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// This module can be used for power-aware simulations, with control signals driven
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// directly by UPF signals.
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//
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// ## Goal:
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// In a memory with multiple banks that support power gating and retention,
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// each bank’s addressing must ensure that interleaving remains intact. During retention
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// or power-off states, only contiguous addresses should be switched.
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// The memory should always appear as a set of contiguous addresses, with no gaps in the
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// address mapping.
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// This module is responsible for managing the correct memory addressing
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//
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module mem_multibank_pwrgate #(
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parameter int unsigned NumWords = 32'd1024, // Number of Words in data array
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parameter int unsigned DataWidth = 32'd128, // Data signal width
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parameter int unsigned ByteWidth = 32'd8, // Width of a data byte
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parameter int unsigned NumPorts = 32'd2, // Number of read and write ports
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parameter int unsigned Latency = 32'd1, // Latency when the read data is available
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parameter int unsigned NumLogicBanks = 32'd1, // Logic bank for Power Management
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parameter SimInit = "none", // Simulation initialization
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parameter bit PrintSimCfg = 1'b0, // Print configuration
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parameter ImplKey = "none", // Reference to specific implementation
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// DEPENDENT PARAMETERS, DO NOT OVERWRITE!
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parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
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parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div
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parameter type addr_t = logic [AddrWidth-1:0],
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parameter type data_t = logic [DataWidth-1:0],
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parameter type be_t = logic [BeWidth-1:0]
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// input ports
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input logic [ NumPorts-1:0] req_i, // request
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input logic [ NumPorts-1:0] we_i, // write enable
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input addr_t [ NumPorts-1:0] addr_i, // request address
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input data_t [ NumPorts-1:0] wdata_i, // write data
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input be_t [ NumPorts-1:0] be_i, // write byte enable
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input logic [NumLogicBanks-1:0] deepsleep_i, // deep sleep enable
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input logic [NumLogicBanks-1:0] powergate_i, // power gate enable
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// output ports
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output data_t [ NumPorts-1:0] rdata_o // read data
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);
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// Implementation type for Power Gating and Deppesleep ports
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typedef struct packed {
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logic deepsleep;
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logic powergate;
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} impl_in_t;
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if (NumLogicBanks == 32'd0) begin : gen_no_logic_bank
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$fatal("Error: %d logic banks are not supported", NumLogicBanks);
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end else if (NumLogicBanks == 32'd1) begin : gen_simple_sram
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tc_sram_impl #(
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.NumWords (NumWords),
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.DataWidth (DataWidth),
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.ByteWidth (ByteWidth),
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.NumPorts (NumPorts),
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.Latency (Latency),
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.SimInit (SimInit),
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.PrintSimCfg(PrintSimCfg),
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.ImplKey (ImplKey),
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.impl_in_t (impl_in_t),
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.impl_out_t (impl_in_t)
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) i_tc_sram_impl (
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.clk_i,
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.rst_ni,
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.impl_i({deepsleep_i, powergate_i}),
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.impl_o(),
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.req_i,
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.we_i,
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.addr_i,
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.wdata_i,
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.be_i,
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.rdata_o
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);
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end else begin : gen_logic_bank // block: gen_simple_sram
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localparam int unsigned LogicBankSize = NumWords / NumLogicBanks;
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localparam int unsigned BankSelWidth = (NumLogicBanks > 32'd1) ? $clog2(
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NumLogicBanks
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) : 32'd1;
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if (LogicBankSize != 2 ** (AddrWidth - BankSelWidth))
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$fatal("Logic Bank size is not a power of two: UNSUPPORTED ");
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// Signals from/to logic banks
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logic [NumLogicBanks-1:0][ NumPorts-1:0] req_cut;
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logic [NumLogicBanks-1:0][ NumPorts-1:0] we_cut;
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logic [NumLogicBanks-1:0][ NumPorts-1:0][AddrWidth-BankSelWidth-1:0] addr_cut;
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data_t [NumLogicBanks-1:0][ NumPorts-1:0] wdata_cut;
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be_t [NumLogicBanks-1:0][ NumPorts-1:0] be_cut;
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data_t [NumLogicBanks-1:0][ NumPorts-1:0] rdata_cut;
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// Signals to select the right bank
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logic [ NumPorts-1:0][BankSelWidth-1:0] bank_sel;
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logic [NumPorts-1:0][Latency-1:0][BankSelWidth-1:0] out_mux_sel_d, out_mux_sel_q;
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// Identify bank looking at the BankSelWidth-th MSBs of the Address
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for (genvar PortIdx = 0; PortIdx < NumPorts; PortIdx++) begin : gen_bank_sel
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assign bank_sel[PortIdx] = addr_i[PortIdx][AddrWidth-1-:BankSelWidth];
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end
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// Read Data Mux Logic:
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//
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// If the memory has Latency != 0, the read data will arive after a certain delay.
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// During this time, the bank_select signal must be stored in order to
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// correctly select the output bank after the expected latency.
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if (Latency == 32'd0) begin : gen_no_latency
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for (genvar PortIdx = 0; PortIdx < NumPorts; PortIdx++) begin : gen_read_mux_signals
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assign rdata_o[PortIdx] = rdata_cut[bank_sel[PortIdx]][PortIdx];
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end
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end else begin : gen_read_latency
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always_comb begin
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for (int PortIdx = 0; PortIdx < NumPorts; PortIdx++) begin : gen_read_mux_signals
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rdata_o[PortIdx] = rdata_cut[out_mux_sel_q[PortIdx][0]][PortIdx];
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for (int shift_idx = 0; shift_idx < (Latency - 1); shift_idx++) begin : gen_shift
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out_mux_sel_d[PortIdx][shift_idx] = out_mux_sel_q[PortIdx][shift_idx+1];
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end
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out_mux_sel_d[PortIdx][Latency-1] = bank_sel[PortIdx];
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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for (int PortIdx = 0; PortIdx < NumPorts; PortIdx++) begin
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if (!rst_ni) begin
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out_mux_sel_q[PortIdx] = '0;
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end else begin
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for (int shift_idx = 0; shift_idx < Latency; shift_idx++) begin
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out_mux_sel_q[PortIdx][shift_idx] = out_mux_sel_d[PortIdx][shift_idx];
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end
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end
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end
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end
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end : gen_read_latency
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// Write data Mux Logic
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//
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for (genvar BankIdx = 0; BankIdx < NumLogicBanks; BankIdx++) begin : gen_logic_bank
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for (genvar PortIdx = 0; PortIdx < NumPorts; PortIdx++) begin
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// DEMUX the input signals to the correct logic bank
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// Assign req channel to the correct logic bank
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assign req_cut[BankIdx][PortIdx] = req_i[PortIdx] && (bank_sel[PortIdx] == BankIdx);
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// Assign lowest part of the address to the correct logic bank
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assign addr_cut[BankIdx][PortIdx] = req_cut[BankIdx][PortIdx] ? addr_i[PortIdx][AddrWidth-BankSelWidth-1:0] : '0;
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// Assign data to the correct logic bank
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assign wdata_cut[BankIdx][PortIdx] = req_cut[BankIdx][PortIdx] ? wdata_i[PortIdx] : '0;
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assign we_cut[BankIdx][PortIdx] = req_cut[BankIdx][PortIdx] ? we_i[PortIdx] : '0;
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assign be_cut[BankIdx][PortIdx] = req_cut[BankIdx][PortIdx] ? be_i[PortIdx] : '0;
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end
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tc_sram_impl #(
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.NumWords (LogicBankSize),
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.DataWidth (DataWidth),
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.ByteWidth (ByteWidth),
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.NumPorts (NumPorts),
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.Latency (Latency),
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.SimInit (SimInit),
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.PrintSimCfg(PrintSimCfg),
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.ImplKey (ImplKey),
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.impl_in_t (impl_in_t),
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.impl_out_t (impl_in_t)
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) i_tc_sram_impl (
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.clk_i,
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.rst_ni,
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.impl_i ({deepsleep_i[BankIdx], powergate_i[BankIdx]}),
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.impl_o (),
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.req_i (req_cut[BankIdx]),
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.we_i (we_cut[BankIdx]),
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.addr_i (addr_cut[BankIdx]),
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.wdata_i(wdata_cut[BankIdx]),
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.be_i (be_cut[BankIdx]),
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.rdata_o(rdata_cut[BankIdx])
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);
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end
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end
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// Trigger warnings when power signals (deepsleep_i and powergate_i) are not connected.
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// Usually those signals must be linked through the UPF.
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`ifndef VERILATOR
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`ifndef TARGET_SYNTHESIS
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initial begin
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assert (!$isunknown(deepsleep_i))
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else $warning("deepsleep_i has some unconnected signals");
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assert (!$isunknown(powergate_i))
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else $warning("powergate_i has some unconnected signals");
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end
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`endif
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`endif
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endmodule //endmodule: mem_multibank_pwrgate

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