treewide: Optimizations for faster Verilator simulation (#259)

* rr_arb_tree: Add Verilator pragmas to split tree node signals

This enables Verilator optimizations as it now understands there are no
combinatorial loops. For the Cheshire SoC, this can reduce simulation
time by around 3%.

* lzc: Add Verilator pragmas to split tree node signals

This enables Verilator optimizations as it now understands there are no
combinatorial loops. For the Cheshire SoC, this can reduce simulation
time by around 2.5%.

* lzc: Optimize reversing of input vector for Verilator speedup

In case the vector is not flipped, using a direct assignment can lead to
an approximately 2% decrease in total system simulation time (measured
using the Cheshire SoC).

* cb_filter: Logic simplification for Verilator speed-up

This decreases total simulation time of the Cheshire SoC by around 1.8%.

Author: MaxWipfli

src/cb_filter.sv

@@ -230,10 +230,8 @@ module hash_block #(
   // output assignment
   always_comb begin : proc_hash_or
     indicator_o = '0;
-    for (int unsigned i = 0; i < (2**HashWidth); i++) begin
-      for (int unsigned j = 0; j < NoHashes; j++) begin
-        indicator_o[i] = indicator_o[i] | hashes[j][i];
-      end
+    for (int unsigned j = 0; j < NoHashes; j++) begin
+      indicator_o = indicator_o | hashes[j];
     end
   end
 

src/lzc.sv

@@ -46,16 +46,21 @@ module lzc #(
   `endif
 
     logic [WIDTH-1:0][NumLevels-1:0] index_lut;
-    logic [2**NumLevels-1:0] sel_nodes;
-    logic [2**NumLevels-1:0][NumLevels-1:0] index_nodes;
+    logic [2**NumLevels-1:0] sel_nodes                  /* verilator split_var */;
+    logic [2**NumLevels-1:0][NumLevels-1:0] index_nodes /* verilator split_var */;
 
     logic [WIDTH-1:0] in_tmp;
 
-    // reverse vector if required
-    always_comb begin : flip_vector
-      for (int unsigned i = 0; i < WIDTH; i++) begin
-        in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i];
+    if (MODE) begin : g_flip
+      // Mode 1 (leading zero): flip input vector
+      always_comb begin : flip_vector
+        for (int unsigned i = 0; i < WIDTH; i++) begin
+          in_tmp[i] = in_i[WIDTH-1-i];
+        end
       end
+    end else begin
+      // Mode 0 (trailing zero)
+      assign in_tmp = in_i;
     end
 
     for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut

src/rr_arb_tree.sv

@@ -121,11 +121,13 @@ module rr_arb_tree #(
   end else begin : gen_arbiter
     localparam int unsigned NumLevels = unsigned'($clog2(NumIn));
 
-    /* verilator lint_off UNOPTFLAT */
-    idx_t    [2**NumLevels-2:0] index_nodes; // used to propagate the indices
-    DataType [2**NumLevels-2:0] data_nodes;  // used to propagate the data
-    logic    [2**NumLevels-2:0] gnt_nodes;   // used to propagate the grant to masters
-    logic    [2**NumLevels-2:0] req_nodes;   // used to propagate the requests to slave
+    /* verilator lint_off SPLITVAR */  // disable warning that is issued if bitwidth is 1
+    idx_t    [2**NumLevels-2:0] index_nodes /* verilator split_var */; // used to propagate the indices
+    DataType [2**NumLevels-2:0] data_nodes  /* verilator split_var */; // used to propagate the data
+    logic    [2**NumLevels-2:0] gnt_nodes   /* verilator split_var */; // used to propagate the grant to masters
+    logic    [2**NumLevels-2:0] req_nodes   /* verilator split_var */; // used to propagate the requests to slave
+    /* verilator lint_on SPLITVAR */
+
     /* lint_off */
     idx_t                       rr_q;
     logic [NumIn-1:0]           req_d;