Add comments from reviewer

- change `payload_t` to `data_t`
- replace inline if with always comb block
- add rr_distributor to src_files

Author: micprog

src/rr_distributor.sv

@@ -16,28 +16,28 @@
 module rr_distributor # (
     /// Number of outputs to distribute to.
     parameter int unsigned NumOut    = 1,
-    /// Data width of the payload in bits. Not needed if `payload_t` is overwritten.
+    /// Data width of the payload in bits. Not needed if `data_t` is overwritten.
     parameter int unsigned Width     = 1,
     /// Data type of the payload, can be overwritten with a custom type. Only use of `Width`.
-    parameter type         payload_t = logic [Width-1:0],
+    parameter type         data_t = logic [Width-1:0],
     /// Dependent parameter, do **not** overwrite.
     /// Width of the selected index
-    parameter int unsigned IdxWidth  = (NumOut > 32'd1) ? unsigned'($clog2(NumOut)) : 32'd1,
+    parameter int unsigned IdxWidth  = cf_math_pkg::idx_width(NumOut),
     /// Dependent parameter, do **not** overwrite.
     /// type of the selected index
     parameter type         idx_t     = logic [IdxWidth-1:0]
 ) (
-    input  logic                  clk_i,
-    input  logic                  rst_ni,
+    input  logic               clk_i,
+    input  logic               rst_ni,
     // input stream
-    input  logic                  valid_i,
-    output logic                  ready_o,
-    input  payload_t              payload_i,
+    input  logic               valid_i,
+    output logic               ready_o,
+    input  data_t              payload_i,
     // output stream
-    output logic     [NumOut-1:0] valid_o,
-    input  logic     [NumOut-1:0] ready_i,
-    output payload_t [NumOut-1:0] payload_o,
-    output idx_t                  sel_o
+    output logic  [NumOut-1:0] valid_o,
+    input  logic  [NumOut-1:0] ready_i,
+    output data_t [NumOut-1:0] payload_o,
+    output idx_t               sel_o
 );
 
     if (NumOut == 1) begin : gen_bypass
@@ -49,8 +49,16 @@ module rr_distributor # (
         idx_t rr_d, rr_q;
         logic one_ready;
 
-        assign rr_d = (valid_i & one_ready) ?
-            ((rr_q == idx_t'(NumOut-1)) ? '0 : rr_q + 1'b1) : rr_q;
+        always_comb begin : rr_next
+            rr_d = rr_q;
+            if (valid_i && one_ready) begin
+                if (rr_q == idx_t'(NumOut - 1)) begin
+                    rr_d = '0;
+                end else begin
+                    rr_d = rr_q + 1'b1;
+                end
+            end
+        end
 
         assign one_ready = |ready_i;
 

src_files.yml

@@ -27,6 +27,7 @@ common_cells_all:
     - src/plru_tree.sv
     - src/popcount.sv
     - src/rr_arb_tree.sv
+    - src/rr_distributor.sv
     - src/rstgen_bypass.sv
     - src/serial_deglitch.sv
     - src/shift_reg.sv