sw: change success exit code to 0

Author: ezelioli

rtl/tb_croc_soc.sv

@@ -285,6 +285,8 @@ module tb_croc_soc #(
     endtask
 
     // Wait for termination signal and get return code
+    // Poll bit zero of core status register which signals end of computation
+    // Bits 1 to 31 contain the application's return value
     task automatic jtag_wait_for_eoc(output bit [31:0] exit_code);
         automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0};
         jtag_write(dm::SBCS, sbcs, 0, 1);
@@ -294,7 +296,11 @@ module tb_croc_soc #(
             jtag_dbg.wait_idle(20);
             jtag_dbg.read_dmi_exp_backoff(dm::SBData0, exit_code);
         end while (exit_code == 0);
-        $display("@%t | [JTAG] Simulation finished: return code 0x%0h", $time, exit_code);
+        exit_code >>= 1;
+        if (exit_code)
+            $display("@%t | [JTAG] Simulation finished: FAIL (return code 0x%0h)", $time, exit_code);
+        else
+            $display("@%t | [JTAG] Simulation finished: SUCCESS", $time);
         $finish();
     endtask
 

sw/crt0.S

@@ -32,6 +32,11 @@ _start:
   li      x15, 0
   call main
 _eoc:
-  la      t0, status
-  sw      a0, 0(t0)
+  # Write status register in SoC control regs
+  # Bit 0 signals end of computation
+  # Bits 31:1 contain return code
+  slli    t0, a0, 1
+  ori     t0, t0, 1
+  la      t1, status
+  sw      t0, 0(t1)
   wfi

sw/helloworld.c

@@ -82,5 +82,5 @@ int main() {
     sleep_ms(10);
     printf("Tock\n");
     uart_write_flush();
-    return 1;
+    return 0;
 }