rtl: fix whitespace lint

phsauter · phsauter · commit 145af2b6c14e · 2026-02-19T00:13:45.000+01:00
diff --git a/ihp13/tc_clk.sv b/ihp13/tc_clk.sv
@@ -80,4 +80,4 @@ module tc_clk_gating #(
     assign clk_o = clk_i;
   end
 
-endmodule
+endmodule
diff --git a/ihp13/tc_sram_impl.sv b/ihp13/tc_sram_impl.sv
@@ -121,11 +121,11 @@ module tc_sram_impl #(
   // Generate desired cuts
   if (NumWords == 64 && DataWidth == 64 && P1L1) begin: gen_64x64xBx1
     logic [63:0] wdata64, rdata64, bm64;
-    
+
     assign rdata_o = rdata64;
     assign wdata64 = wdata_i;
     assign bm64    = bm;
-    
+
 
     RM_IHPSG13_1P_64x64_c2_bm_bist i_cut (
       .A_CLK   ( clk_i    ),
@@ -142,7 +142,7 @@ module tc_sram_impl #(
 
   end else if (NumWords == 256 & DataWidth == 64 & P1L1) begin : gen_256x64xBx1
     logic [63:0] wdata64, rdata64, bm64;
-    
+
     assign rdata_o = rdata64;
     assign wdata64 = wdata_i;
     assign bm64    = bm;
@@ -162,7 +162,7 @@ module tc_sram_impl #(
 
   end else if (NumWords == 512 & DataWidth == 64 & P1L1) begin : gen_512x64xBx1
     logic [63:0] wdata64, rdata64, bm64;
-    
+
     assign rdata_o = rdata64;
     assign wdata64 = wdata_i;
     assign bm64    = bm;
@@ -182,7 +182,7 @@ module tc_sram_impl #(
 
   end else if (NumWords == 1024 & DataWidth == 64 & P1L1) begin : gen_1024x64xBx1
     logic [63:0] wdata64, rdata64, bm64;
-    
+
     assign rdata_o = rdata64;
     assign wdata64 = wdata_i;
     assign bm64    = bm;
@@ -202,7 +202,7 @@ module tc_sram_impl #(
 
   end else if (NumWords == 2048 & DataWidth == 64 & P1L1) begin : gen_2048x64xBx1
     logic [63:0] wdata64, rdata64, bm64;
-    
+
     assign rdata_o = rdata64;
     assign wdata64 = wdata_i;
     assign bm64    = bm;
@@ -346,7 +346,7 @@ module tc_sram_impl #(
 
   end else if (NumWords == 2048 & DataWidth == 64 & P1L1) begin : gen_2048x64xBx1
     logic [63:0] wdata64, rdata64, bm64;
-    
+
     assign rdata_o = rdata64;
     assign wdata64 = wdata_i;
     assign bm64    = bm;
diff --git a/rtl/bootrom/bootrom.sv b/rtl/bootrom/bootrom.sv
@@ -17,17 +17,17 @@
 /// Trap handler dispatches to SRAM function pointer table at 0x1000_0000.
 /// Source: bootrom.S
 module bootrom #(
-	/// The OBI configuration for all ports.
-	parameter obi_pkg::obi_cfg_t ObiCfg = obi_pkg::ObiDefaultConfig,
-	/// OBI request type
-	parameter type obi_req_t = logic,
-	/// OBI response type
-	parameter type obi_rsp_t = logic
+    /// The OBI configuration for all ports.
+    parameter obi_pkg::obi_cfg_t ObiCfg = obi_pkg::ObiDefaultConfig,
+    /// OBI request type
+    parameter type obi_req_t = logic,
+    /// OBI response type
+    parameter type obi_rsp_t = logic
 ) (
-	input  logic     clk_i,
-	input  logic     rst_ni,
-	input  obi_req_t obi_req_i,
-	output obi_rsp_t obi_rsp_o
+    input  logic     clk_i,
+    input  logic     rst_ni,
+    input  obi_req_t obi_req_i,
+    output obi_rsp_t obi_rsp_o
 );
 
     //-----------------------------------------------------------------------------------
@@ -130,21 +130,21 @@ module bootrom #(
     // --------------------------------------------------------------------------
     localparam int unsigned WordAddressWidth = 10; // 12-bit byte address
 
-	logic                        we_d, we_q;
-	logic                        req_d, req_q;
-	logic [ObiCfg.IdWidth-1:0]   id_d, id_q;
-	logic [WordAddressWidth-1:0] word_addr_d, word_addr_q;
+    logic                        we_d, we_q;
+    logic                        req_d, req_q;
+    logic [ObiCfg.IdWidth-1:0]   id_d, id_q;
+    logic [WordAddressWidth-1:0] word_addr_d, word_addr_q;
 
-	assign req_d       = obi_req_i.req;
-	assign we_d        = obi_req_i.a.we;
-	assign id_d        = obi_req_i.a.aid;
-	assign word_addr_d = obi_req_i.a.addr[WordAddressWidth+2-1:2];
+    assign req_d       = obi_req_i.req;
+    assign we_d        = obi_req_i.a.we;
+    assign id_d        = obi_req_i.a.aid;
+    assign word_addr_d = obi_req_i.a.addr[WordAddressWidth+2-1:2];
 
-	// Latch request for one-cycle response
-	`FF(req_q, req_d, '0, clk_i, rst_ni)
-	`FF(we_q, we_d, '0, clk_i, rst_ni)
-	`FF(id_q, id_d, '0, clk_i, rst_ni)
-	`FF(word_addr_q, word_addr_d, '0, clk_i, rst_ni)
+    // Latch request for one-cycle response
+    `FF(req_q, req_d, '0, clk_i, rst_ni)
+    `FF(we_q, we_d, '0, clk_i, rst_ni)
+    `FF(id_q, id_d, '0, clk_i, rst_ni)
+    `FF(word_addr_q, word_addr_d, '0, clk_i, rst_ni)
 
     // --------------------------------------------------------------------------
     // Mask-based ROM decode:
@@ -161,9 +161,9 @@ module bootrom #(
     assign rom_select = word_addr_q[WordAddressWidth-1 -: 4];
     assign rom_idx    = word_addr_q[5:0];
 
-	always_comb begin
-		rom_rdata = 32'h0000_0000;
-		rom_error = 1'b1;
+    always_comb begin
+        rom_rdata = 32'h0000_0000;
+        rom_error = 1'b1;
 
         case (rom_select)
             4'b0000: rom_size  = StartRomWords;
diff --git a/rtl/core_wrap.sv b/rtl/core_wrap.sv
@@ -52,7 +52,7 @@ module core_wrap import croc_pkg::*; #() (
 
   // lowest 8 bits are ignored internally
   logic[31:0] ibex_boot_addr;
-  assign ibex_boot_addr = boot_addr_i & 32'hFFFFFF00; 
+  assign ibex_boot_addr = boot_addr_i & 32'hFFFFFF00;
 
   // CV-X-IF tie-offs (extension disabled)
   cve2_pkg::x_issue_resp_t x_issue_resp;
@@ -94,7 +94,7 @@ module core_wrap import croc_pkg::*; #() (
     .instr_err_i,
 
     // Data memory interface:
-    .data_req_o, 
+    .data_req_o,
     .data_gnt_i,
     .data_rvalid_i,
     .data_we_o,
@@ -129,7 +129,7 @@ module core_wrap import croc_pkg::*; #() (
     .dm_halt_addr_i      ( DebugHaltAddress      ),
     .dm_exception_addr_i ( DebugExceptionAddress ),
     .crash_dump_o        ( ),
-    
+
     .fetch_enable_i,
     .core_busy_o
   );
diff --git a/rtl/croc_chip.sv b/rtl/croc_chip.sv
@@ -63,7 +63,7 @@ module croc_chip import croc_pkg::*; #() (
   inout wire VSS,
   inout wire VDDIO,
   inout wire VSSIO
-); 
+);
     logic soc_clk_i;
     logic soc_rst_ni;
     logic soc_ref_clk_i;
@@ -79,8 +79,8 @@ module croc_chip import croc_pkg::*; #() (
 
     localparam int unsigned GpioCount = 32;
 
-    logic [GpioCount-1:0] soc_gpio_i;             
-    logic [GpioCount-1:0] soc_gpio_o;            
+    logic [GpioCount-1:0] soc_gpio_i;
+    logic [GpioCount-1:0] soc_gpio_o;
     logic [GpioCount-1:0] soc_gpio_out_en_o; // Output enable signal; 0 -> input, 1 -> output
 
     sg13g2_IOPadIn        pad_clk_i        (.pad(clk_i),        .p2c(soc_clk_i));
@@ -174,8 +174,8 @@ module croc_chip import croc_pkg::*; #() (
     .uart_rx_i      ( soc_uart_rx_i ),
     .uart_tx_o      ( soc_uart_tx_o ),
 
-    .gpio_i         ( soc_gpio_i        ),             
-    .gpio_o         ( soc_gpio_o        ),            
+    .gpio_i         ( soc_gpio_i        ),
+    .gpio_o         ( soc_gpio_o        ),
     .gpio_out_en_o  ( soc_gpio_out_en_o )
   );
 
diff --git a/rtl/croc_domain.sv b/rtl/croc_domain.sv
@@ -28,9 +28,9 @@ module croc_domain import croc_pkg::*; #(
   output logic [GpioCount-1:0] gpio_out_en_o, // Output enable signal; 0 -> input, 1 -> output
 
   output logic [GpioCount-1:0] gpio_in_sync_o, // synchronized GPIO inputs
-  
+
   /// User OBI interface
-  /// User as subordinate (from core to user module) 
+  /// User as subordinate (from core to user module)
   /// Address space 0x2000_0000 - 0x8000_0000
   output sbr_obi_req_t user_sbr_obi_req_o,
   input  sbr_obi_rsp_t user_sbr_obi_rsp_i,
@@ -465,7 +465,7 @@ module croc_domain import croc_pkg::*; #(
     .sbr_ports_req_i  ( {core_dma_I_R_obi_req, core_dma_D_W_obi_req, dbg_req_obi_req, user_mgr_obi_req_i } ),
     .sbr_ports_rsp_o  ( {core_dma_I_R_obi_rsp, core_dma_D_W_obi_rsp, dbg_req_obi_rsp, user_mgr_obi_rsp_o } ),
     // connections between crossbar and subordinates
-    .mgr_ports_req_o  ( all_sbr_obi_req ), 
+    .mgr_ports_req_o  ( all_sbr_obi_req ),
     .mgr_ports_rsp_i  ( all_sbr_obi_rsp ),
 
     .addr_map_i       ( croc_addr_map ),
@@ -612,11 +612,11 @@ module croc_domain import croc_pkg::*; #(
   ) i_uart (
     .clk_i,
     .rst_ni,
-   
+
     .obi_req_i ( uart_obi_req ),
     .obi_rsp_o ( uart_obi_rsp ),
-    .irq_o     ( uart_irq     ), 
-    .irq_no    ( ), 
+    .irq_o     ( uart_irq     ),
+    .irq_no    ( ),
 
     .rxd_i     ( uart_rx_i ),
     .txd_o     ( uart_tx_o ),
@@ -626,7 +626,7 @@ module croc_domain import croc_pkg::*; #(
     .dsr_ni    ( 1'b1 ),
     .ri_ni     ( 1'b1 ),
     .cd_ni     ( 1'b1 ),
-    .rts_no    ( ), 
+    .rts_no    ( ),
     .dtr_no    ( ),
     .out1_no   ( ),
     .out2_no   ( )
@@ -641,10 +641,10 @@ module croc_domain import croc_pkg::*; #(
   ) i_gpio (
     .clk_i,
     .rst_ni,
-    .gpio_i,                     
-    .gpio_o,                   
-    .gpio_out_en_o,          
-    .gpio_in_sync_o,       
+    .gpio_i,
+    .gpio_o,
+    .gpio_out_en_o,
+    .gpio_in_sync_o,
     .interrupt_o    ( gpio_irq     ),
     .obi_req_i      ( gpio_obi_req ),
     .obi_rsp_o      ( gpio_obi_rsp )
diff --git a/rtl/croc_soc.sv b/rtl/croc_soc.sv
@@ -68,8 +68,8 @@ croc_domain #(
   .uart_rx_i,
   .uart_tx_o,
 
-  .gpio_i,             
-  .gpio_o,            
+  .gpio_i,
+  .gpio_o,
   .gpio_out_en_o,
 
   .gpio_in_sync_o ( gpio_in_sync ),
diff --git a/rtl/gpio/gpio.sv b/rtl/gpio/gpio.sv
@@ -34,7 +34,7 @@ module gpio #(
     /// the output enable of the corresponding IO Pad.
     /// 0 -> input, 1 -> output.
     output logic [GpioCount-1:0] gpio_out_en_o,
-    /// Synchronized GPIO input signals. 
+    /// Synchronized GPIO input signals.
     // Provides the gpio_i signal synchronized to clk_i to other modules.
     output logic [GpioCount-1:0] gpio_in_sync_o,
     /// GPIO interrupt line. The interrupt line is asserted for one clk_i
diff --git a/rtl/gpio/gpio_reg_top.sv b/rtl/gpio/gpio_reg_top.sv
@@ -104,7 +104,7 @@ module gpio_reg_top import gpio_reg_pkg::*; #(
   // register signals
   gpio_reg_fields_t reg_d, reg_q;
   `FF(reg_q, reg_d, '0, clk_i, rst_ni)
-  
+
   gpio_reg_fields_t new_reg; // new value of regs if there is no OBI transaction
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -145,7 +145,7 @@ module gpio_reg_top import gpio_reg_pkg::*; #(
     // control logic interaction for each GPIO
     for(int unsigned idx=0; idx < GpioCount; idx++) begin
       new_reg.in[idx]     = hw2reg[idx].sync_in; // input is updated
-      new_reg.toggle[idx] = '0;                  // toggle clears itself 
+      new_reg.toggle[idx] = '0;                  // toggle clears itself
 
       // update OUT from hw2reg if set to valid
       new_reg.out[idx]    = hw2reg[idx].out_valid ? hw2reg[idx].out : reg_q.out[idx];
diff --git a/rtl/idma/croc_idma.sv b/rtl/idma/croc_idma.sv
@@ -171,7 +171,7 @@ module croc_idma #(
         obi_cfg_rsp_o.r.rdata = reg_read_data;
         obi_cfg_rsp_o.rvalid  = req_q;
         obi_cfg_rsp_o.gnt     = word_addr_d == NEXT_ID_OFFSET ?
-                                obi_cfg_req_i.req & job_req_ready : obi_cfg_req_i.req; 
+                                obi_cfg_req_i.req & job_req_ready : obi_cfg_req_i.req;
     end
 
     // OBI Storage
diff --git a/rtl/idma/idma_obi_write.sv b/rtl/idma/idma_obi_write.sv
@@ -117,7 +117,7 @@ module idma_obi_write #(
         // create back pressure on the b channel if the higher parts of the DMA
         // cannot accept more write responses
         write_req_o.rready  = w_dp_ready_i;
-        
+
         if (MaskInvalidData) begin : gen_mask_invalid_data
             write_req_o.a.addr  = aw_req_i.obi.a_chan.addr;
             write_req_o.a.aid   = aw_req_i.obi.a_chan.aid;
diff --git a/rtl/soc_ctrl/soc_ctrl_regs.sv b/rtl/soc_ctrl/soc_ctrl_regs.sv
@@ -48,7 +48,7 @@ module soc_ctrl_regs #(
 
   always_comb begin : obi_response
     obi_rsp_o         = '0;
-    obi_rsp_o.gnt     = 1'b1; 
+    obi_rsp_o.gnt     = 1'b1;
     obi_rsp_o.rvalid  = obi_req_q.req;
     obi_rsp_o.r.err   = err_q;
     obi_rsp_o.r.rid   = obi_req_q.a.aid;
diff --git a/rtl/test/tb_croc_pkg.sv b/rtl/test/tb_croc_pkg.sv
@@ -13,7 +13,7 @@ package tb_croc_pkg;
   localparam realtime ClkPeriodJtag = 50ns;    // 20 MHz
   localparam realtime ClkPeriodRef  = 30518ns; // 32 KiHz
 
-  // Number of clock cycles the reset is applied 
+  // Number of clock cycles the reset is applied
   // for at the beginnig of the simulation
   localparam int unsigned RstCycles = 1;
 
diff --git a/rtl/test/tb_croc_soc.sv b/rtl/test/tb_croc_soc.sv
@@ -55,7 +55,7 @@ module tb_croc_soc #(
   ////////////
   //  VIP   //
   ////////////
-  // Verification IP 
+  // Verification IP
   // - drives clocks and resets
   // - provides helper tasks and functions for JTAG, namely:
   //   - jtag_load_hex: loads a hex file into the DUT's memory
diff --git a/rtl/user_domain.sv b/rtl/user_domain.sv
@@ -13,7 +13,7 @@ module user_domain import user_pkg::*; import croc_pkg::*; #(
   input  logic      ref_clk_i,
   input  logic      rst_ni,
   input  logic      testmode_i,
-  
+
   input  sbr_obi_req_t user_sbr_obi_req_i, // User Sbr (rsp_o), Croc Mgr (req_i)
   output sbr_obi_rsp_t user_sbr_obi_rsp_o,
 
@@ -24,7 +24,7 @@ module user_domain import user_pkg::*; import croc_pkg::*; #(
   output logic [NumExternalIrqs-1:0] interrupts_o // interrupts to core
 );
 
-  assign interrupts_o = '0;  
+  assign interrupts_o = '0;
 
 
   //////////////////////
@@ -42,7 +42,7 @@ module user_domain import user_pkg::*; import croc_pkg::*; #(
   // ----------------------------------------------------------------------------------------------
   // User Subordinate Buses
   // ----------------------------------------------------------------------------------------------
-  
+
   // collection of signals from the demultiplexer
   sbr_obi_req_t [NumDemuxSbr-1:0] all_user_sbr_obi_req;
   sbr_obi_rsp_t [NumDemuxSbr-1:0] all_user_sbr_obi_rsp;
diff --git a/rtl/user_pkg.sv b/rtl/user_pkg.sv
@@ -12,7 +12,7 @@ package user_pkg;
   //////////////////
   // User Manager //
   //////////////////
-  
+
   // None
 
 
@@ -36,6 +36,6 @@ package user_pkg;
   // All addresses outside the defined address rules go to the error subordinate
 
   // +1 for additional OBI error
-  localparam int unsigned NumDemuxSbr = $size(user_addr_map) + 1; 
+  localparam int unsigned NumDemuxSbr = $size(user_addr_map) + 1;
 
 endpackage
diff --git a/xilinx/hw/croc_xilinx.sv b/xilinx/hw/croc_xilinx.sv
diff --git a/xilinx/hw/fan_ctrl.sv b/xilinx/hw/fan_ctrl.sv
