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ezelioliezelioli
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rtl: add OBI SoC control register file
1 parent 9f3e3ac commit 2b8b0fd

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6 files changed

+175
-54
lines changed

6 files changed

+175
-54
lines changed

‎Bender.yml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ sources:
3030

3131
- rtl/croc_pkg.sv
3232
- rtl/user_pkg.sv
33-
- rtl/soc_ctrl/soc_ctrl_reg_pkg.sv
33+
- rtl/soc_ctrl/soc_ctrl_regs_pkg.sv
3434
- rtl/gpio/gpio_reg_pkg.sv
3535
# add your design files containing anything but modules (packages) here
3636

@@ -39,7 +39,7 @@ sources:
3939
files:
4040
# Level 1
4141
- rtl/core_wrap.sv
42-
- rtl/soc_ctrl/soc_ctrl_reg_top.sv
42+
- rtl/soc_ctrl/soc_ctrl_regs.sv
4343
- rtl/gpio/gpio_reg_top.sv
4444
- rtl/gpio/gpio.sv
4545
# Level 2

‎croc.flist‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -155,10 +155,10 @@ ihp13/tc_clk.sv
155155
ihp13/tc_sram_impl.sv
156156
rtl/croc_pkg.sv
157157
rtl/user_pkg.sv
158-
rtl/soc_ctrl/soc_ctrl_reg_pkg.sv
158+
rtl/soc_ctrl/soc_ctrl_regs_pkg.sv
159159
rtl/gpio/gpio_reg_pkg.sv
160160
rtl/core_wrap.sv
161-
rtl/soc_ctrl/soc_ctrl_reg_top.sv
161+
rtl/soc_ctrl/soc_ctrl_regs.sv
162162
rtl/gpio/gpio_reg_top.sv
163163
rtl/gpio/gpio.sv
164164
rtl/croc_domain.sv

‎rtl/croc_domain.sv‎

Lines changed: 11 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -467,57 +467,21 @@ module croc_domain import croc_pkg::*; #(
467467
);
468468

469469
// SoC Control
470-
reg_req_t soc_ctrl_reg_req;
471-
reg_rsp_t soc_ctrl_reg_rsp;
472-
473-
periph_to_reg #(
474-
.AW ( SbrObiCfg.AddrWidth ),
475-
.DW ( SbrObiCfg.DataWidth ),
476-
.BW ( 8 ),
477-
.IW ( SbrObiCfg.IdWidth ),
478-
.req_t ( reg_req_t ),
479-
.rsp_t ( reg_rsp_t )
480-
) i_soc_ctrl_translate (
481-
.clk_i,
482-
.rst_ni,
470+
logic fetch_en_reg;
471+
assign fetch_enable = fetch_en_i | fetch_en_reg;
483472

484-
.req_i ( soc_ctrl_obi_req.req ),
485-
.add_i ( soc_ctrl_obi_req.a.addr ),
486-
.wen_i ( ~soc_ctrl_obi_req.a.we ),
487-
.wdata_i ( soc_ctrl_obi_req.a.wdata ),
488-
.be_i ( soc_ctrl_obi_req.a.be ),
489-
.id_i ( soc_ctrl_obi_req.a.aid ),
490-
491-
.gnt_o ( soc_ctrl_obi_rsp.gnt ),
492-
.r_rdata_o ( soc_ctrl_obi_rsp.r.rdata ),
493-
.r_opc_o ( soc_ctrl_obi_rsp.r.err ),
494-
.r_id_o ( soc_ctrl_obi_rsp.r.rid ),
495-
.r_valid_o ( soc_ctrl_obi_rsp.rvalid ),
496-
497-
.reg_req_o ( soc_ctrl_reg_req ),
498-
.reg_rsp_i ( soc_ctrl_reg_rsp )
499-
);
500-
assign soc_ctrl_obi_rsp.r.r_optional = '0;
501-
502-
soc_ctrl_reg_pkg::soc_ctrl_reg2hw_t soc_ctrl_reg2hw;
503-
soc_ctrl_reg_pkg::soc_ctrl_hw2reg_t soc_ctrl_hw2reg;
504-
assign fetch_enable = soc_ctrl_reg2hw.fetchen.q | fetch_en_i;
505-
assign boot_addr = soc_ctrl_reg2hw.bootaddr.q;
506-
assign sram_impl = soc_ctrl_reg2hw.sram_dly;
507-
assign soc_ctrl_hw2reg = '0;
508-
509-
soc_ctrl_reg_top #(
510-
.reg_req_t ( reg_req_t ),
511-
.reg_rsp_t ( reg_rsp_t ),
512-
.BootAddrDefault ( SramBaseAddr )
473+
soc_ctrl_regs #(
474+
.obi_req_t ( sbr_obi_req_t ),
475+
.obi_rsp_t ( sbr_obi_rsp_t ),
476+
.BootAddrDefault ( SramBaseAddr )
513477
) i_soc_ctrl (
514478
.clk_i,
515479
.rst_ni,
516-
.reg_req_i ( soc_ctrl_reg_req ),
517-
.reg_rsp_o ( soc_ctrl_reg_rsp ),
518-
.reg2hw ( soc_ctrl_reg2hw ),
519-
.hw2reg ( soc_ctrl_hw2reg ),
520-
.devmode_i ( 1'b0 )
480+
.obi_req_i ( soc_ctrl_obi_req ),
481+
.obi_rsp_o ( soc_ctrl_obi_rsp ),
482+
.boot_addr_o ( boot_addr ),
483+
.fetch_en_o ( fetch_en_reg ),
484+
.sram_dly_o ( sram_impl )
521485
);
522486

523487
// UART

‎rtl/soc_ctrl/soc_ctrl_regs.sv‎

Lines changed: 136 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,136 @@
1+
// Copyright 2025 ETH Zurich and University of Bologna.
2+
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
3+
// SPDX-License-Identifier: SHL-0.51
4+
//
5+
// Authors:
6+
// - Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
7+
8+
module soc_ctrl_regs #(
9+
parameter type obi_req_t = logic,
10+
parameter type obi_rsp_t = logic,
11+
parameter int unsigned BootAddrDefault = 32'h0
12+
) (
13+
input logic clk_i,
14+
input logic rst_ni,
15+
input obi_req_t obi_req_i,
16+
output obi_rsp_t obi_rsp_o,
17+
// To hardware
18+
output logic [31:0] boot_addr_o,
19+
output logic fetch_en_o,
20+
output logic sram_dly_o
21+
);
22+
23+
import soc_ctrl_regs_pkg::*;
24+
25+
// Registers
26+
logic [31:0] boot_addr_d, boot_addr_q;
27+
logic fetch_en_d, fetch_en_q;
28+
logic [31:0] core_status_d, core_status_q;
29+
logic boot_mode_d, boot_mode_q;
30+
logic sram_dly_d, sram_dly_q;
31+
32+
// Internal signals
33+
obi_req_t obi_req_d, obi_req_q;
34+
logic [31:0] rdata_d, rdata_q;
35+
logic err_d, err_q;
36+
37+
// Latch OBI request
38+
assign obi_req_d = obi_req_i;
39+
40+
// Output assignment
41+
assign boot_addr_o = boot_addr_q;
42+
assign fetch_en_o = fetch_en_q;
43+
assign sram_dly_o = sram_dly_q;
44+
45+
always_comb begin : obi_response
46+
obi_rsp_o = '0;
47+
obi_rsp_o.gnt = 1'b1;
48+
obi_rsp_o.rvalid = obi_req_q.req;
49+
obi_rsp_o.r.err = err_q;
50+
obi_rsp_o.r.rid = obi_req_q.a.aid;
51+
obi_rsp_o.r.rdata = rdata_q;
52+
end
53+
54+
always_comb begin : read_write_fsm
55+
rdata_d = '0;
56+
err_d = '0;
57+
boot_addr_d = boot_addr_q;
58+
fetch_en_d = fetch_en_q;
59+
core_status_d = core_status_q;
60+
boot_mode_d = boot_mode_q;
61+
sram_dly_d = sram_dly_q;
62+
63+
if (obi_req_i.req) begin
64+
65+
if (obi_req_i.a.we) begin : write
66+
automatic logic [31:0] wdata = obi_req_i.a.wdata;
67+
unique case (obi_req_i.a.addr[IntAddrWidth-1:0])
68+
SOC_CTRL_BOOTADDR_OFFSET: begin
69+
boot_addr_d = wdata;
70+
end
71+
SOC_CTRL_FETCHEN_OFFSET: begin
72+
fetch_en_d = wdata[0];
73+
end
74+
SOC_CTRL_CORESTATUS_OFFSET: begin
75+
core_status_d = wdata;
76+
end
77+
SOC_CTRL_BOOTMODE_OFFSET: begin
78+
boot_mode_d = wdata[0];
79+
end
80+
SOC_CTRL_SRAM_DLY_OFFSET: begin
81+
sram_dly_d = wdata[0];
82+
end
83+
default: begin
84+
err_d = 1'b1;
85+
end
86+
endcase
87+
88+
end else begin : read
89+
unique case (obi_req_i.a.addr[IntAddrWidth-1:0])
90+
SOC_CTRL_BOOTADDR_OFFSET: begin
91+
rdata_d = boot_addr_q;
92+
end
93+
SOC_CTRL_FETCHEN_OFFSET: begin
94+
rdata_d = {31'h0, fetch_en_q};
95+
end
96+
SOC_CTRL_CORESTATUS_OFFSET: begin
97+
rdata_d = core_status_q;
98+
end
99+
SOC_CTRL_BOOTMODE_OFFSET: begin
100+
rdata_d = {31'h0, boot_mode_q};
101+
end
102+
SOC_CTRL_SRAM_DLY_OFFSET: begin
103+
rdata_d = {31'b0, sram_dly_q};
104+
end
105+
default: begin
106+
err_d = 1'b1;
107+
end
108+
endcase
109+
end
110+
111+
end
112+
end
113+
114+
always_ff @(posedge clk_i or negedge rst_ni) begin
115+
if (~rst_ni) begin
116+
boot_addr_q <= BootAddrDefault;
117+
fetch_en_q <= '0;
118+
core_status_q <= '0;
119+
boot_mode_q <= '0;
120+
sram_dly_q <= '0;
121+
obi_req_q <= '0;
122+
rdata_q <= '0;
123+
err_q <= '0;
124+
end else begin
125+
boot_addr_q <= boot_addr_d;
126+
fetch_en_q <= fetch_en_d;
127+
core_status_q <= core_status_d;
128+
boot_mode_q <= boot_mode_d;
129+
sram_dly_q <= sram_dly_d;
130+
obi_req_q <= obi_req_d;
131+
rdata_q <= rdata_d;
132+
err_q <= err_d;
133+
end
134+
end
135+
136+
endmodule

‎rtl/soc_ctrl/soc_ctrl_regs_pkg.sv‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
// Copyright 2025 ETH Zurich and University of Bologna.
2+
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
3+
// SPDX-License-Identifier: SHL-0.51
4+
//
5+
// Authors:
6+
// - Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
7+
8+
package soc_ctrl_regs_pkg;
9+
10+
// Internal address width. We only need 5 bits to
11+
// store the offsets of the five registers implemented.
12+
localparam int unsigned IntAddrWidth = 5;
13+
14+
// Register offsets
15+
parameter logic [IntAddrWidth-1:0] SOC_CTRL_BOOTADDR_OFFSET = 5'h00;
16+
parameter logic [IntAddrWidth-1:0] SOC_CTRL_FETCHEN_OFFSET = 5'h04;
17+
parameter logic [IntAddrWidth-1:0] SOC_CTRL_CORESTATUS_OFFSET = 5'h08;
18+
parameter logic [IntAddrWidth-1:0] SOC_CTRL_BOOTMODE_OFFSET = 5'h0c;
19+
parameter logic [IntAddrWidth-1:0] SOC_CTRL_SRAM_DLY_OFFSET = 5'h10;
20+
21+
endpackage

‎rtl/tb_croc_soc.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,11 +44,11 @@ module tb_croc_soc #(
4444

4545
// Register addresses
4646
localparam bit [31:0] BootAddrAddr = croc_pkg::SocCtrlAddrOffset
47-
+ soc_ctrl_reg_pkg::SOC_CTRL_BOOTADDR_OFFSET;
47+
+ soc_ctrl_regs_pkg::SOC_CTRL_BOOTADDR_OFFSET;
4848
localparam bit [31:0] FetchEnAddr = croc_pkg::SocCtrlAddrOffset
49-
+ soc_ctrl_reg_pkg::SOC_CTRL_FETCHEN_OFFSET;
49+
+ soc_ctrl_regs_pkg::SOC_CTRL_FETCHEN_OFFSET;
5050
localparam bit [31:0] CoreStatusAddr = croc_pkg::SocCtrlAddrOffset
51-
+ soc_ctrl_reg_pkg::SOC_CTRL_CORESTATUS_OFFSET;
51+
+ soc_ctrl_regs_pkg::SOC_CTRL_CORESTATUS_OFFSET;
5252

5353
/////////////////////////////
5454
// Command Line Arguments //

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