treewide: remove unnecessary make fragments

Author: ezelioli

Makefile

@@ -6,13 +6,7 @@
 # - Philippe Sauter <[email protected]>
 
 # Tools
-BENDER	  ?= bender
-PYTHON3   ?= python3
-VERILATOR ?= /foss/tools/bin/verilator
-YOSYS     ?= yosys
-OPENROAD  ?= openroad
-KLAYOUT   ?= klayout
-VSIM      ?= vsim
+BENDER ?= bender
 
 # Directories
 # directory of the path to the last called Makefile (this one)
@@ -59,81 +53,6 @@ sw: $(SW_HEX)
 
 .PHONY: software sw
 
-##################
-# RTL Simulation #
-##################
-# Questasim/Modelsim/vsim
-VLOG_ARGS  = -svinputport=compat
-VSIM_ARGS  = -t 1ns -voptargs=+acc
-VSIM_ARGS += -suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386
-
-vsim/compile_rtl.tcl: Bender.lock Bender.yml
-	$(BENDER) script vsim -t rtl -t vsim -t simulation -t verilator -DSYNTHESIS -DSIMULATION  --vlog-arg="$(VLOG_ARGS)" > $@
-
-vsim/compile_netlist.tcl: Bender.lock Bender.yml
-	$(BENDER) script vsim -t ihp13 -t vsim -t simulation -t verilator -t netlist_yosys -DSYNTHESIS -DSIMULATION > $@
-
-## Simulate RTL using Questasim/Modelsim/vsim
-vsim: vsim/compile_rtl.tcl $(SW_HEX)
-	rm -rf vsim/work
-	cd vsim; $(VSIM) -c -do "source compile_rtl.tcl; exit"
-	cd vsim; $(VSIM) +binary="$(realpath $(SW_HEX))" -gui tb_croc_soc $(VSIM_ARGS)
-
-## Simulate netlist using Questasim/Modelsim/vsim
-vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_chip_yosys_debug.v
-	rm -rf vsim/work
-	cd vsim; $(VSIM) -c -do "source compile_netlist.tcl; source compile_tech.tcl; exit"
-	cd vsim; $(VSIM) -gui tb_croc_soc $(VSIM_ARGS)
-
-
-# Verilator
-# Turn off style warnings and well-defined SystemVerilog warnings that should be part of -Wno-style
-VERILATOR_ARGS = -Wno-fatal -Wno-style \
-	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
-
-VERILATOR_ARGS += --binary -j 0
-VERILATOR_ARGS += --timing --autoflush --trace-fst --trace-threads 2 --trace-structs
-VERILATOR_ARGS +=  --unroll-count 1 --unroll-stmts 1
-VERILATOR_ARGS += --x-assign fast --x-initial fast
-VERILATOR_CFLAGS += -O3 -march=native -mtune=native
-
-verilator/croc.f: Bender.lock Bender.yml
-	$(BENDER) script verilator -t rtl -t verilator -t cve2_include_tracer -DSYNTHESIS -DVERILATOR -DTRACE_EXECUTION > $@
-
-verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
-	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f
-
-## Simulate RTL using Verilator
-verilator: verilator/obj_dir/Vtb_croc_soc
-	cd verilator; obj_dir/Vtb_croc_soc +binary="$(realpath $(SW_HEX))" | tee croc.log
-
-.PHONY: verilator vsim vsim-yosys
-
-
-####################
-# Open Source Flow #
-####################
-# Bender manages the different IPs and can be used to generate file-lists for synthesis
-TOP_DESIGN     ?= croc_chip
-DUT_DESIGN	   ?= croc_soc
-BENDER_TARGETS ?= asic ihp13 rtl synthesis
-SV_DEFINES     ?= VERILATOR SYNTHESIS COMMON_CELLS_ASSERTS_OFF
-
-## Generate croc.flist used to read design in yosys
-yosys-flist: Bender.lock Bender.yml rtl/*/Bender.yml
-	$(BENDER) script flist-plus $(foreach t,$(BENDER_TARGETS),-t $(t)) $(foreach d,$(SV_DEFINES),-D $(d)=1) > $(PROJ_DIR)/croc.flist
-
-include yosys/yosys.mk
-include openroad/openroad.mk
-
-klayout/croc_chip.gds: $(OR_OUT)/croc.def klayout/*.sh klayout/*.py
-	./klayout/def2gds.sh
-
-## Generate merged .gds from openroads .def output
-klayout: klayout/croc_chip.gds
-
-.PHONY: klayout yosys-flist
-
 
 #################
 # Documentation #
@@ -162,12 +81,6 @@ help: Makefile
 
 ## Delete generated files and directories
 clean: 
-	rm -f $(SV_FLIST)
-	rm -f klayout/croc_chip.gds
-	rm -rf verilator/obj_dir/
-	rm -f verilator/croc.f
-	rm -f verilator/croc.vcd
-	$(MAKE) ys_clean
-	$(MAKE) or_clean
+	$(MAKE) -C sw clean
 
 .PHONY: clean