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rtl: simplify configuration in croc_pkg
1 parent 762875c commit 5609be2

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6 files changed

+132
-152
lines changed

6 files changed

+132
-152
lines changed

rtl/core_wrap.sv

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,9 @@ module core_wrap import croc_pkg::*; #() (
4444
output logic core_busy_o
4545
);
4646

47+
// Base address of the debug module in the memory map.
48+
localparam bit [31:0] DebugAddrOffset = get_periph_addr_rule(PeriphDebug);
49+
4750
// lowest 8 bits are ignored internally
4851
logic[31:0] ibex_boot_addr;
4952
assign ibex_boot_addr = boot_addr_i & 32'hFFFFFF00;
@@ -53,23 +56,23 @@ module core_wrap import croc_pkg::*; #() (
5356
`else
5457
cve2_core #(
5558
`endif
56-
.PMPEnable ( 1'b0 ),
57-
.PMPGranularity ( 0 ),
58-
.PMPNumRegions ( 4 ),
59-
.MHPMCounterNum ( 0 ),
60-
.MHPMCounterWidth ( 40 ),
61-
.RV32E ( 0 ),
62-
.RV32M ( cve2_pkg::RV32MNone ),
63-
.RV32B ( cve2_pkg::RV32BNone ),
64-
.DbgTriggerEn ( 1'b1 ),
65-
.DbgHwBreakNum ( 1 ),
66-
.DmHaltAddr ( DebugAddrOffset + dm::HaltAddress[31:0] ),
67-
.DmExceptionAddr ( DebugAddrOffset + dm::ExceptionAddress[31:0] )
59+
.PMPEnable ( 1'b0 ),
60+
.PMPGranularity ( 0 ),
61+
.PMPNumRegions ( 4 ),
62+
.MHPMCounterNum ( 0 ),
63+
.MHPMCounterWidth ( 40 ),
64+
.RV32E ( 0 ),
65+
.RV32M ( cve2_pkg::RV32MNone ),
66+
.RV32B ( cve2_pkg::RV32BNone ),
67+
.DbgTriggerEn ( 1'b1 ),
68+
.DbgHwBreakNum ( 1 ),
69+
.DmHaltAddr ( DebugAddrOffset + dm::HaltAddress[31:0] ),
70+
.DmExceptionAddr ( DebugAddrOffset + dm::ExceptionAddress[31:0] )
6871
) i_ibex (
6972
.clk_i,
7073
.rst_ni,
7174
.test_en_i ( test_enable_i ),
72-
.hart_id_i ( HartId ),
75+
.hart_id_i ( 32'd0 ),
7376
.boot_addr_i ( ibex_boot_addr ),
7477

7578
// Instruction Memory Interface:

rtl/croc_domain.sv

Lines changed: 21 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,8 @@
66
// - Philippe Sauter <phsauter@iis.ee.ethz.ch>
77

88
module croc_domain import croc_pkg::*; #(
9-
parameter int unsigned GpioCount = 16
9+
parameter int unsigned GpioCount = 16,
10+
parameter int unsigned NumExternalIrqs = 4
1011
) (
1112
input logic clk_i,
1213
input logic rst_ni,
@@ -94,8 +95,8 @@ module croc_domain import croc_pkg::*; #(
9495
// Subordinate buses out of crossbar
9596
// ----------------------------------
9697
// Main xbar subordinate buses, must align with addr map indices!
97-
sbr_obi_req_t [NumXbarSbr-1:0] all_sbr_obi_req;
98-
sbr_obi_rsp_t [NumXbarSbr-1:0] all_sbr_obi_rsp;
98+
sbr_obi_req_t [NumXbarSubordinates-1:0] all_sbr_obi_req;
99+
sbr_obi_rsp_t [NumXbarSubordinates-1:0] all_sbr_obi_rsp;
99100

100101
// user bus defined in module port
101102

@@ -305,21 +306,21 @@ module croc_domain import croc_pkg::*; #(
305306
// -----------------
306307

307308
obi_xbar #(
308-
.SbrPortObiCfg ( MgrObiCfg ),
309-
.MgrPortObiCfg ( SbrObiCfg ),
310-
.sbr_port_obi_req_t ( mgr_obi_req_t ),
311-
.sbr_port_a_chan_t ( mgr_obi_a_chan_t ),
312-
.sbr_port_obi_rsp_t ( mgr_obi_rsp_t ),
313-
.sbr_port_r_chan_t ( mgr_obi_r_chan_t ),
314-
.mgr_port_obi_req_t ( sbr_obi_req_t ),
315-
.mgr_port_obi_rsp_t ( sbr_obi_rsp_t ),
316-
.NumSbrPorts ( NumXbarManagers ),
317-
.NumMgrPorts ( NumXbarSbr ),
318-
.NumMaxTrans ( 2 ),
319-
.NumAddrRules ( NumXbarSbrRules ),
320-
.addr_map_rule_t ( addr_map_rule_t ),
321-
.UseIdForRouting ( 1'b0 ),
322-
.Connectivity ( '1 )
309+
.SbrPortObiCfg ( MgrObiCfg ),
310+
.MgrPortObiCfg ( SbrObiCfg ),
311+
.sbr_port_obi_req_t ( mgr_obi_req_t ),
312+
.sbr_port_a_chan_t ( mgr_obi_a_chan_t ),
313+
.sbr_port_obi_rsp_t ( mgr_obi_rsp_t ),
314+
.sbr_port_r_chan_t ( mgr_obi_r_chan_t ),
315+
.mgr_port_obi_req_t ( sbr_obi_req_t ),
316+
.mgr_port_obi_rsp_t ( sbr_obi_rsp_t ),
317+
.NumSbrPorts ( NumXbarManagers ),
318+
.NumMgrPorts ( NumXbarSubordinates ),
319+
.NumMaxTrans ( 2 ),
320+
.NumAddrRules ( $size(croc_addr_map) ),
321+
.addr_map_rule_t ( addr_map_rule_t ),
322+
.UseIdForRouting ( 1'b0 ),
323+
.Connectivity ( '1 )
323324
) i_main_xbar (
324325
.clk_i,
325326
.rst_ni,
@@ -419,7 +420,7 @@ module croc_domain import croc_pkg::*; #(
419420

420421
addr_decode #(
421422
.NoIndices ( NumPeriphs ),
422-
.NoRules ( NumPeriphRules ),
423+
.NoRules ( $size(periph_addr_map) ),
423424
.addr_t ( logic[SbrObiCfg.DataWidth-1:0] ),
424425
.rule_t ( addr_map_rule_t ),
425426
.Napot ( 1'b0 )
@@ -473,7 +474,7 @@ module croc_domain import croc_pkg::*; #(
473474
soc_ctrl_regs #(
474475
.obi_req_t ( sbr_obi_req_t ),
475476
.obi_rsp_t ( sbr_obi_rsp_t ),
476-
.BootAddrDefault ( SramBaseAddr )
477+
.BootAddrDefault ( BootAddr )
477478
) i_soc_ctrl (
478479
.clk_i,
479480
.rst_ni,

rtl/croc_pkg.sv

Lines changed: 79 additions & 108 deletions
Original file line numberDiff line numberDiff line change
@@ -9,40 +9,24 @@
99
`include "obi/typedef.svh"
1010

1111
package croc_pkg;
12-
13-
localparam int unsigned HartId = 32'd0;
14-
15-
// Default JTAG ID code type
16-
typedef struct packed {
12+
// PULP Platform manufacturer and default Croc part number
13+
localparam struct packed {
1714
bit [ 3:0] version;
1815
bit [15:0] part_num;
1916
bit [10:0] manufacturer;
2017
bit _one;
21-
} jtag_idcode_t;
22-
23-
// PULP Platform manufacturer and default Cheshire part number
24-
localparam bit [10:0] JtagPulpManufacturer = 11'h6d9;
25-
localparam bit [15:0] JtagCrocPartNum = 16'hC0C5;
26-
localparam bit [ 3:0] JtagCrocVersion = 4'h0;
27-
localparam jtag_idcode_t PulpJtagIdCode = '{
28-
_one : 1,
29-
manufacturer : JtagPulpManufacturer,
30-
part_num : JtagCrocPartNum,
31-
version : JtagCrocVersion
18+
} PulpJtagIdCode = '{
19+
_one: 1'b1,
20+
manufacturer: 11'h6d9,
21+
part_num: 16'hC0C5,
22+
version: 4'h0
3223
};
3324

34-
typedef enum logic {
35-
Jtag = 1'b0
36-
} bootmode_e;
37-
38-
// Number of additional interrupts coming into croc_domain and going to the core
39-
localparam int unsigned NumExternalIrqs = 4;
40-
41-
4225
///////////////////////
4326
// Address Maps ///
4427
///////////////////////
45-
// ideally compatible with: https://pulp-platform.github.io/cheshire/um/arch/#memory-map
28+
// ideally compatible with:
29+
// https://pulp-platform.github.io/cheshire/um/arch/#memory-map
4630

4731
// Address map data type
4832
typedef struct packed {
@@ -52,79 +36,43 @@ package croc_pkg;
5236
} addr_map_rule_t;
5337

5438

55-
////////////////////////////////////////
56-
// Croc Main interconnect addressing ///
57-
////////////////////////////////////////
58-
59-
localparam bit [31:0] PeriphBaseAddr = 32'h0000_0000;
60-
localparam bit [31:0] PeriphAddrRange = 32'h1000_0000;
39+
////////////////////////////////
40+
// Main Crossbar Address Map ///
41+
////////////////////////////////
6142

62-
localparam bit [31:0] SramBaseAddr = 32'h1000_0000;
6343
localparam int unsigned NumSramBanks = 32'd2;
6444
localparam int unsigned SramBankNumWords = 512;
6545
localparam int unsigned SramBankAddrWidth = cf_math_pkg::idx_width(SramBankNumWords);
66-
localparam int unsigned SramAddrRange = NumSramBanks*SramBankNumWords*4;
6746

68-
localparam bit [31:0] UserBaseAddr = 32'h2000_0000;
69-
localparam bit [31:0] UserAddrRange = 32'h6000_0000;
70-
71-
localparam int unsigned NumCrocDomainSubordinates = 2 + NumSramBanks; // Peripherals + Memory + User Domain
72-
73-
localparam int unsigned NumXbarManagers = 4; // Debug module, Core Instr, Core Data, User Domain
74-
localparam int unsigned NumXbarSbrRules = NumCrocDomainSubordinates; // number of address rules in the decoder
75-
localparam int unsigned NumXbarSbr = NumXbarSbrRules + 1; // additional OBI error, used for signal arrays
47+
localparam bit [31:0] UserBaseAddr = 32'h2000_0000; // use as base for your IPs
48+
localparam bit [31:0] BootAddr = 32'h1000_0000; // start of SRAM banks
7649

7750
// Enum for bus indices
7851
typedef enum int {
7952
XbarError = 0,
8053
XbarPeriph = 1,
81-
XbarBank0 = 2,
82-
XbarUser = 2 + NumSramBanks
54+
XbarUser = 2,
55+
XbarBank0 = 3
8356
} croc_xbar_outputs_e;
8457

85-
// generate the address rules dependent on the number of SRAM banks
86-
function automatic addr_map_rule_t [NumXbarSbrRules-1:0] gen_xbar_addr_rules();
87-
addr_map_rule_t [NumXbarSbrRules-1:0] ret;
88-
ret[0] = '{ idx: XbarPeriph,
89-
start_addr: PeriphBaseAddr,
90-
end_addr: PeriphBaseAddr+PeriphAddrRange};
91-
92-
for (int i = 0; i < NumSramBanks; i++) begin
93-
ret[i+1] = '{ idx: XbarBank0+i,
94-
start_addr: SramBaseAddr + ( i * SramBankNumWords*4),
95-
end_addr: SramBaseAddr + ((i+1) * SramBankNumWords*4)};
96-
97-
ret[NumXbarSbrRules-1] = '{ idx: XbarUser,
98-
start_addr: UserBaseAddr,
99-
end_addr: UserBaseAddr+UserAddrRange};
100-
end
101-
return ret;
102-
endfunction
103-
104-
localparam addr_map_rule_t [NumXbarSbrRules-1:0] croc_addr_map = gen_xbar_addr_rules();
105-
106-
107-
/////////////////////////////
108-
// Peripheral address map ///
109-
/////////////////////////////
110-
111-
localparam bit [31:0] DebugAddrOffset = 32'h0000_0000;
112-
localparam bit [31:0] DebugAddrRange = 32'h0004_0000;
113-
114-
localparam bit [31:0] SocCtrlAddrOffset = 32'h0300_0000;
115-
localparam bit [31:0] SocCtrlAddrRange = 32'h0000_1000;
58+
// Main interconnect address map (order: periph, user, SRAM banks)
59+
localparam addr_map_rule_t [3:0] croc_addr_map = '{
60+
'{ idx: XbarPeriph, start_addr: 32'h0000_0000, end_addr: 32'h1000_0000 },
61+
'{ idx: XbarUser, start_addr: 32'h2000_0000, end_addr: 32'h8000_0000 },
62+
'{ idx: XbarBank0, start_addr: 32'h1000_0000, end_addr: 32'h1000_0800 },
63+
'{ idx: XbarBank0+1, start_addr: 32'h1000_0800, end_addr: 32'h1000_1000 }
64+
};
11665

117-
localparam bit [31:0] UartAddrOffset = 32'h0300_2000;
118-
localparam bit [31:0] UartAddrRange = 32'h0000_1000;
66+
// Debug module, Core Instr, Core Data, User Domain
67+
localparam int unsigned NumXbarManagers = 4;
11968

120-
localparam bit [31:0] GpioAddrOffset = 32'h0300_5000;
121-
localparam bit [31:0] GpioAddrRange = 32'h0000_1000;
69+
// +1 for additional OBI error
70+
localparam int unsigned NumXbarSubordinates = $size(croc_addr_map) + 1;
12271

123-
localparam bit [31:0] TimerAddrOffset = 32'h0300_A000;
124-
localparam bit [31:0] TimerAddrRange = 32'h0000_1000;
12572

126-
localparam int unsigned NumPeriphRules = 5;
127-
localparam int unsigned NumPeriphs = NumPeriphRules + 1; // additional OBI error
73+
/////////////////////////////////
74+
// Peripheral Mux Address Map ///
75+
/////////////////////////////////
12876

12977
// Enum for bus indices
13078
typedef enum int {
@@ -136,34 +84,57 @@ package croc_pkg;
13684
PeriphTimer = 5
13785
} periph_outputs_e;
13886

139-
localparam addr_map_rule_t [NumPeriphRules-1:0] periph_addr_map = '{ // 0: OBI Error (default)
140-
'{ idx: PeriphDebug, start_addr: DebugAddrOffset, end_addr: DebugAddrOffset + DebugAddrRange}, // 1: Debug
141-
'{ idx: PeriphSocCtrl, start_addr: SocCtrlAddrOffset, end_addr: SocCtrlAddrOffset + SocCtrlAddrRange}, // 2: SoC control
142-
'{ idx: PeriphUart, start_addr: UartAddrOffset, end_addr: UartAddrOffset + UartAddrRange}, // 3: UART
143-
'{ idx: PeriphGpio, start_addr: GpioAddrOffset, end_addr: GpioAddrOffset + GpioAddrRange}, // 4: GPIO
144-
'{ idx: PeriphTimer, start_addr: TimerAddrOffset, end_addr: TimerAddrOffset + TimerAddrRange} // 5: Timer
87+
localparam addr_map_rule_t [4:0] periph_addr_map = '{
88+
'{ idx: PeriphDebug, start_addr: 32'h0000_0000, end_addr: 32'h0004_0000 },
89+
'{ idx: PeriphSocCtrl, start_addr: 32'h0300_0000, end_addr: 32'h0300_1000 },
90+
'{ idx: PeriphUart, start_addr: 32'h0300_2000, end_addr: 32'h0300_3000 },
91+
'{ idx: PeriphGpio, start_addr: 32'h0300_5000, end_addr: 32'h0300_6000 },
92+
'{ idx: PeriphTimer, start_addr: 32'h0300_A000, end_addr: 32'h0300_B000 }
14593
};
14694

147-
// OBI is configured as 32 bit data, 32 bit address width
95+
// +1 for additional OBI error
96+
localparam int unsigned NumPeriphs = $size(periph_addr_map) + 1;
97+
98+
// Use these functions to get the address from the index enum
99+
function automatic addr_map_rule_t get_croc_addr_rule(croc_xbar_outputs_e port);
100+
bit [31:0] addr = '0;
101+
for (int unsigned i = 0; i < $size(croc_addr_map); i++) begin
102+
if (croc_xbar_outputs_e'(croc_addr_map[i].idx) == port) begin
103+
return croc_addr_map[i].start_addr;
104+
end
105+
end
106+
return addr;
107+
endfunction
108+
109+
function automatic addr_map_rule_t get_periph_addr_rule(periph_outputs_e port);
110+
bit [31:0] addr = '0;
111+
for (int unsigned i = 0; i < $size(periph_addr_map); i++) begin
112+
if (periph_outputs_e'(periph_addr_map[i].idx) == port) begin
113+
return periph_addr_map[i].start_addr;
114+
end
115+
end
116+
return addr;
117+
endfunction
148118

149119

150120
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
151-
121+
// OBI is configured as 32 bit data, 32 bit address width
122+
152123
// Usually we would use the typedef.svh macros to define interconnects from parameters.
153124
// To make it easier to understand we instead write them out here,
154125
// at the end of the block in a comment you can find the equivalent using the macros.
155126

156127
/// OBI managers configuration (from a manager into the interconnect)
157128
localparam obi_pkg::obi_cfg_t MgrObiCfg = '{
158-
UseRReady: 1'b0,
159-
CombGnt: 1'b0,
160-
AddrWidth: 32,
161-
DataWidth: 32,
162-
IdWidth: 1,
163-
Integrity: 1'b0,
164-
BeFull: 1'b1,
165-
OptionalCfg: '0
166-
};
129+
UseRReady: 1'b0,
130+
CombGnt: 1'b0,
131+
AddrWidth: 32,
132+
DataWidth: 32,
133+
IdWidth: 1,
134+
Integrity: 1'b0,
135+
BeFull: 1'b1,
136+
OptionalCfg: '0
137+
};
167138
/// OBI Manager <-> Xbar address channel
168139
typedef struct packed {
169140
logic [ MgrObiCfg.AddrWidth-1:0] addr;
@@ -194,15 +165,15 @@ package croc_pkg;
194165

195166
/// OBI subordinate configuration (from the interconnect to a subordinate device)
196167
localparam obi_pkg::obi_cfg_t SbrObiCfg = '{
197-
UseRReady: 1'b0,
198-
CombGnt: 1'b0,
199-
AddrWidth: 32,
200-
DataWidth: 32,
201-
IdWidth: 1 + cf_math_pkg::idx_width(NumXbarManagers),
202-
Integrity: 1'b0,
203-
BeFull: 1'b1,
204-
OptionalCfg: '0
205-
};
168+
UseRReady: 1'b0,
169+
CombGnt: 1'b0,
170+
AddrWidth: 32,
171+
DataWidth: 32,
172+
IdWidth: 1 + cf_math_pkg::idx_width(NumXbarManagers),
173+
Integrity: 1'b0,
174+
BeFull: 1'b1,
175+
OptionalCfg: '0
176+
};
206177
/// OBI Xbar <-> Subordinate address channel
207178
typedef struct packed {
208179
logic [ SbrObiCfg.AddrWidth-1:0] addr;

rtl/croc_soc.sv

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -57,11 +57,13 @@ sbr_obi_rsp_t user_sbr_obi_rsp;
5757
mgr_obi_req_t user_mgr_obi_req;
5858
mgr_obi_rsp_t user_mgr_obi_rsp;
5959

60+
localparam int unsigned NumExternalIrqs = 4;
6061
logic [NumExternalIrqs-1:0] interrupts;
61-
logic [GpioCount-1:0] gpio_in_sync;
62+
logic [ GpioCount-1:0] gpio_in_sync;
6263

6364
croc_domain #(
64-
.GpioCount( GpioCount )
65+
.GpioCount ( GpioCount ),
66+
.NumExternalIrqs ( NumExternalIrqs )
6567
) i_croc (
6668
.clk_i,
6769
.rst_ni ( synced_rst_n ),
@@ -95,7 +97,8 @@ croc_domain #(
9597
);
9698

9799
user_domain #(
98-
.GpioCount( GpioCount )
100+
.GpioCount ( GpioCount ),
101+
.NumExternalIrqs ( NumExternalIrqs )
99102
) i_user (
100103
.clk_i,
101104
.rst_ni ( synced_rst_n ),

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