yosys: add a default croc.flist

fixup flist

Author: phsauter

.gitignore

@@ -1,4 +1,2 @@
-pickle
 .bender
-WORK
-croc.flist
+tmp

Bender.yml

@@ -32,6 +32,7 @@ sources:
   - rtl/user_pkg.sv
   - rtl/soc_ctrl/soc_ctrl_reg_pkg.sv
   - rtl/gpio/gpio_reg_pkg.sv
+  # add your design files containing anything but modules (packages) here
 
     # RTL
   - target: not(netlist_yosys)
@@ -44,6 +45,7 @@ sources:
       # Level 2
       - rtl/croc_domain.sv
       - rtl/user_domain.sv
+      # add your design files with modules here
       # Level 3
       - rtl/croc_soc.sv
 

Makefile

@@ -46,7 +46,7 @@ SW_HEX := sw/bin/helloworld.hex
 $(SW_HEX): sw/*.c sw/*.h sw/*.S sw/*.ld
 	$(MAKE) -C sw/ compile
 
-## Build the helloworld software
+## Build all top-level programs in sw/
 software: $(SW_HEX)
 
 sw: $(SW_HEX)
@@ -88,14 +88,14 @@ VERILATOR_ARGS += --timing --autoflush --trace --trace-structs
 verilator/croc.f: Bender.lock Bender.yml
 	$(BENDER) script verilator -t rtl -t verilator -DSYNTHESIS -DVERILATOR > $@
 
-## Simulate RTL using Verilator
 verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
 	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -CFLAGS "-O0" --top tb_croc_soc -f croc.f
 
+## Simulate RTL using Verilator
 verilator: verilator/obj_dir/Vtb_croc_soc
 	cd verilator; obj_dir/Vtb_croc_soc +binary="$(realpath $(SW_HEX))"
 
-.PHONY: verilator vsim vsim-yosys verilator-yosys
+.PHONY: verilator vsim vsim-yosys
 
 
 ####################
@@ -107,8 +107,8 @@ DUT_DESIGN	   ?= croc_soc
 BENDER_TARGETS ?= asic ihp13 rtl synthesis
 SV_DEFINES     ?= VERILATOR SYNTHESIS COMMON_CELLS_ASSERTS_OFF
 
-# re-generate file list given to yosys-slang frontend
-synth-flist: Bender.lock Bender.yml rtl/*/Bender.yml
+## Generate croc.flist used to read design in yosys
+yosys-flist: Bender.lock Bender.yml rtl/*/Bender.yml
 	$(BENDER) script flist-plus $(foreach t,$(BENDER_TARGETS),-t $(t)) $(foreach d,$(SV_DEFINES),-D $(d)=1) > $(PROJ_DIR)/croc.flist
 
 include yosys/yosys.mk
@@ -117,9 +117,10 @@ include openroad/openroad.mk
 klayout/croc_chip.gds: $(OR_OUT)/croc.def klayout/*.sh klayout/*.py
 	./klayout/def2gds.sh
 
+## Generate merged .gds from openroads .def output
 klayout: klayout/croc_chip.gds
 
-.PHONY: klayout
+.PHONY: klayout yosys-flist
 
 
 #################
@@ -147,6 +148,7 @@ help: Makefile
 # Cleanup #
 ###########
 
+## Delete generated files and directories
 clean: 
 	rm -f $(SV_FLIST)
 	rm -f klayout/croc_chip.gds

README.md

@@ -162,6 +162,17 @@ The most important make targets are documented, you can list them with:
 make help
 ```
 
+### Building on Croc
+To add your own design, we recommend creating a new directory under `rtl/` or put single source files (small designs) into `rtl/user_domain`, then go into `Bender.yml` and add the files in the indicated places.
+This will make Bender aware of the files and any script it contains will contain your design as well.
+
+Then re-generate the default synthesis file-list:
+```sh
+make yosys-flist
+```
+
+If you want to add an existing design and it already containts a `Bender.yml` in its repository, you can add it as a dependency in the `Bender.yml` and reading the guide below.
+
 ## Bender
 The dependency manager [Bender](https://github.com/pulp-platform/bender) is used in most pulp-platform IPs.
 Usually each dependency would be in a seperate repository, each with a `Bender.yml` file to describe where the RTL files are, how you can use this dependency and which additional dependency it has.

croc.flist

@@ -0,0 +1,187 @@
+# Copyright (c) 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Authors:
+# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+# A file list given to the yosys-slang frontend to load the design
+# It contains:
+# - include directores expected from SystemVerilog 'include' statements
+# - defines used in some SystemVerilog files
+#   often used to guard non-synthesisable code or select some implementation
+# - the paths to all source files
+
++incdir+/home/phsauter/repos/croc/rtl/apb/include
++incdir+/home/phsauter/repos/croc/rtl/common_cells/include
++incdir+/home/phsauter/repos/croc/rtl/cve2/include
++incdir+/home/phsauter/repos/croc/rtl/obi/include
++incdir+/home/phsauter/repos/croc/rtl/register_interface/include
++define+TARGET_ASIC
++define+TARGET_FLIST
++define+TARGET_IHP13
++define+TARGET_RTL
++define+TARGET_SYNTHESIS
++define+VERILATOR=1
++define+SYNTHESIS=1
++define+COMMON_CELLS_ASSERTS_OFF=1
+/home/phsauter/repos/croc/rtl/common_cells/binary_to_gray.sv
+/home/phsauter/repos/croc/rtl/common_cells/cb_filter_pkg.sv
+/home/phsauter/repos/croc/rtl/common_cells/cc_onehot.sv
+/home/phsauter/repos/croc/rtl/common_cells/cdc_reset_ctrlr_pkg.sv
+/home/phsauter/repos/croc/rtl/common_cells/cf_math_pkg.sv
+/home/phsauter/repos/croc/rtl/common_cells/clk_int_div.sv
+/home/phsauter/repos/croc/rtl/common_cells/credit_counter.sv
+/home/phsauter/repos/croc/rtl/common_cells/delta_counter.sv
+/home/phsauter/repos/croc/rtl/common_cells/ecc_pkg.sv
+/home/phsauter/repos/croc/rtl/common_cells/edge_propagator_tx.sv
+/home/phsauter/repos/croc/rtl/common_cells/exp_backoff.sv
+/home/phsauter/repos/croc/rtl/common_cells/fifo_v3.sv
+/home/phsauter/repos/croc/rtl/common_cells/gray_to_binary.sv
+/home/phsauter/repos/croc/rtl/common_cells/isochronous_4phase_handshake.sv
+/home/phsauter/repos/croc/rtl/common_cells/isochronous_spill_register.sv
+/home/phsauter/repos/croc/rtl/common_cells/lfsr.sv
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+/home/phsauter/repos/croc/rtl/common_cells/lfsr_8bit.sv
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+/home/phsauter/repos/croc/rtl/common_cells/onehot_to_bin.sv
+/home/phsauter/repos/croc/rtl/common_cells/plru_tree.sv
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+/home/phsauter/repos/croc/rtl/common_cells/rstgen_bypass.sv
+/home/phsauter/repos/croc/rtl/common_cells/serial_deglitch.sv
+/home/phsauter/repos/croc/rtl/common_cells/shift_reg.sv
+/home/phsauter/repos/croc/rtl/common_cells/shift_reg_gated.sv
+/home/phsauter/repos/croc/rtl/common_cells/spill_register_flushable.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_demux.sv
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+/home/phsauter/repos/croc/rtl/common_cells/stream_fork.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_intf.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_join_dynamic.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_mux.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_throttle.sv
+/home/phsauter/repos/croc/rtl/common_cells/sub_per_hash.sv
+/home/phsauter/repos/croc/rtl/common_cells/sync.sv
+/home/phsauter/repos/croc/rtl/common_cells/sync_wedge.sv
+/home/phsauter/repos/croc/rtl/common_cells/unread.sv
+/home/phsauter/repos/croc/rtl/common_cells/read.sv
+/home/phsauter/repos/croc/rtl/common_cells/addr_decode_dync.sv
+/home/phsauter/repos/croc/rtl/common_cells/cdc_2phase.sv
+/home/phsauter/repos/croc/rtl/common_cells/cdc_4phase.sv
+/home/phsauter/repos/croc/rtl/common_cells/clk_int_div_static.sv
+/home/phsauter/repos/croc/rtl/common_cells/addr_decode.sv
+/home/phsauter/repos/croc/rtl/common_cells/addr_decode_napot.sv
+/home/phsauter/repos/croc/rtl/common_cells/multiaddr_decode.sv
+/home/phsauter/repos/croc/rtl/common_cells/cb_filter.sv
+/home/phsauter/repos/croc/rtl/common_cells/cdc_fifo_2phase.sv
+/home/phsauter/repos/croc/rtl/common_cells/clk_mux_glitch_free.sv
+/home/phsauter/repos/croc/rtl/common_cells/counter.sv
+/home/phsauter/repos/croc/rtl/common_cells/ecc_decode.sv
+/home/phsauter/repos/croc/rtl/common_cells/ecc_encode.sv
+/home/phsauter/repos/croc/rtl/common_cells/edge_detect.sv
+/home/phsauter/repos/croc/rtl/common_cells/lzc.sv
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+/home/phsauter/repos/croc/rtl/common_cells/rstgen.sv
+/home/phsauter/repos/croc/rtl/common_cells/spill_register.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_delay.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_fifo.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_fork_dynamic.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_join.sv
+/home/phsauter/repos/croc/rtl/common_cells/cdc_reset_ctrlr.sv
+/home/phsauter/repos/croc/rtl/common_cells/cdc_fifo_gray.sv
+/home/phsauter/repos/croc/rtl/common_cells/fall_through_register.sv
+/home/phsauter/repos/croc/rtl/common_cells/id_queue.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_to_mem.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_arbiter_flushable.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_fifo_optimal_wrap.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_register.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_xbar.sv
+/home/phsauter/repos/croc/rtl/common_cells/cdc_fifo_gray_clearable.sv
+/home/phsauter/repos/croc/rtl/common_cells/cdc_2phase_clearable.sv
+/home/phsauter/repos/croc/rtl/common_cells/mem_to_banks_detailed.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_arbiter.sv
+/home/phsauter/repos/croc/rtl/common_cells/stream_omega_net.sv
+/home/phsauter/repos/croc/rtl/common_cells/mem_to_banks.sv
+/home/phsauter/repos/croc/rtl/apb/apb_pkg.sv
+/home/phsauter/repos/croc/rtl/register_interface/reg_intf.sv
+/home/phsauter/repos/croc/rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv
+/home/phsauter/repos/croc/rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv
+/home/phsauter/repos/croc/rtl/register_interface/periph_to_reg.sv
+/home/phsauter/repos/croc/rtl/register_interface/reg_to_apb.sv
+/home/phsauter/repos/croc/rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv
+/home/phsauter/repos/croc/rtl/register_interface/lowrisc_opentitan/prim_subreg.sv
+/home/phsauter/repos/croc/rtl/apb_uart/slib_clock_div.sv
+/home/phsauter/repos/croc/rtl/apb_uart/slib_counter.sv
+/home/phsauter/repos/croc/rtl/apb_uart/slib_edge_detect.sv
+/home/phsauter/repos/croc/rtl/apb_uart/slib_fifo.sv
+/home/phsauter/repos/croc/rtl/apb_uart/slib_input_filter.sv
+/home/phsauter/repos/croc/rtl/apb_uart/slib_input_sync.sv
+/home/phsauter/repos/croc/rtl/apb_uart/slib_mv_filter.sv
+/home/phsauter/repos/croc/rtl/apb_uart/uart_baudgen.sv
+/home/phsauter/repos/croc/rtl/apb_uart/uart_interrupt.sv
+/home/phsauter/repos/croc/rtl/apb_uart/uart_receiver.sv
+/home/phsauter/repos/croc/rtl/apb_uart/uart_transmitter.sv
+/home/phsauter/repos/croc/rtl/apb_uart/apb_uart.sv
+/home/phsauter/repos/croc/rtl/apb_uart/apb_uart_wrap.sv
+/home/phsauter/repos/croc/rtl/apb_uart/reg_uart_wrap.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_pkg.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_alu.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_compressed_decoder.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_controller.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_counter.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_csr.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_decoder.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_fetch_fifo.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_load_store_unit.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_multdiv_fast.sv
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+/home/phsauter/repos/croc/rtl/cve2/cve2_pmp.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_register_file_ff.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_wb.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_cs_registers.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_ex_block.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_id_stage.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_prefetch_buffer.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_if_stage.sv
+/home/phsauter/repos/croc/rtl/cve2/cve2_core.sv
+/home/phsauter/repos/croc/rtl/obi/obi_pkg.sv
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+/home/phsauter/repos/croc/rtl/obi/obi_rready_converter.sv
+/home/phsauter/repos/croc/rtl/obi/obi_atop_resolver.sv
+/home/phsauter/repos/croc/rtl/obi/obi_demux.sv
+/home/phsauter/repos/croc/rtl/obi/obi_err_sbr.sv
+/home/phsauter/repos/croc/rtl/obi/obi_mux.sv
+/home/phsauter/repos/croc/rtl/obi/obi_sram_shim.sv
+/home/phsauter/repos/croc/rtl/obi/obi_xbar.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dm_pkg.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/debug_rom/debug_rom.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dm_csrs.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dm_mem.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dmi_cdc.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dmi_jtag_tap.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dm_sba.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dm_top.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dmi_jtag.sv
+/home/phsauter/repos/croc/rtl/riscv-dbg/dm_obi_top.sv
+/home/phsauter/repos/croc/rtl/timer_unit/timer_unit_counter.sv
+/home/phsauter/repos/croc/rtl/timer_unit/timer_unit_counter_presc.sv
+/home/phsauter/repos/croc/rtl/timer_unit/apb_timer_unit.sv
+/home/phsauter/repos/croc/rtl/timer_unit/timer_unit.sv
+/home/phsauter/repos/croc/ihp13/tc_clk.sv
+/home/phsauter/repos/croc/ihp13/tc_sram.sv
+/home/phsauter/repos/croc/rtl/croc_pkg.sv
+/home/phsauter/repos/croc/rtl/user_pkg.sv
+/home/phsauter/repos/croc/rtl/soc_ctrl/soc_ctrl_reg_pkg.sv
+/home/phsauter/repos/croc/rtl/gpio/gpio_reg_pkg.sv
+/home/phsauter/repos/croc/rtl/core_wrap.sv
+/home/phsauter/repos/croc/rtl/soc_ctrl/soc_ctrl_reg_top.sv
+/home/phsauter/repos/croc/rtl/gpio/gpio_reg_top.sv
+/home/phsauter/repos/croc/rtl/gpio/gpio.sv
+/home/phsauter/repos/croc/rtl/croc_domain.sv
+/home/phsauter/repos/croc/rtl/user_domain.sv
+/home/phsauter/repos/croc/rtl/croc_soc.sv
+/home/phsauter/repos/croc/rtl/croc_chip.sv
+