openroad: rework floorplan and padring

- move die size def to floorplan.tcl
- move bondpads into OpenROAD die area

Author: phsauter

openroad/scripts/chip.tcl

@@ -48,20 +48,6 @@ report_checks -unconstrained -format end -no_line_splits >> ${report_dir}/${log_
 report_checks -format end -no_line_splits                >> ${report_dir}/${log_id_str}_${proj_name}_checks.rpt
 report_checks -format end -no_line_splits                >> ${report_dir}/${log_id_str}_${proj_name}_checks.rpt
 
-# Size of the chip
-set chipW            1760.0
-set chipH            1760.0
-
-# thickness of annular ring for pads (length of a pad)
-set padRing           180.0
-set coreMargin [expr $padRing + 35]; # space for power ring
-
-utl::report "Initialize Chip"
-initialize_floorplan -die_area "0 0 $chipW $chipH" \
-                     -core_area "$coreMargin $coreMargin [expr $chipW-$coreMargin] [expr $chipH-$coreMargin]" \
-                     -site "CoreSite"
-
-
 utl::report "Connect global nets (power)"
 source scripts/power_connect.tcl
 

openroad/scripts/floorplan.tcl

@@ -26,6 +26,36 @@ foreach inst $insts {
   }
 }
 
+##########################################################################
+# Die and Core Area 
+##########################################################################
+# Dimensions:                          [um]
+#   final chip size (4sqmm) 2000.0 x 2000.0
+#   seal ring thickness       35.0 ,   35.0 x2
+#   bonding pad               70.0 ,   70.0 x2
+#   io cell depth            180.0 ,  180.0 x2
+#   ---------------------------------------
+#   -> OR die area          1930.0 x 1930.0
+#   -> OR core area         1430.0 x 1430.0
+# The sealring is added after OpenROAD
+# hence the OR die area is the final chip size minus the sealring thickness on each side
+
+set chipH    1930; # OR die height (top to bottom)
+set chipW    1930; # OR die width (left to right)
+set padD      180; # pad depth (edge to core)
+set padW       80; # pad width (beachfront)
+set padBond    70; # bonding pad size
+set powerRing  80; # reserved space for power ring
+
+# starting from the outside and working towards the core area on each side
+set coreMargin [expr {$padD + $padBond + $powerRing}];
+
+utl::report "Initialize Chip"
+# coordinates are lower-left x and y, upper-right x and y
+initialize_floorplan -die_area "0 0 $chipW $chipH" \
+                     -core_area "$coreMargin $coreMargin [expr $chipW-$coreMargin] [expr $chipH-$coreMargin]" \
+                     -site "CoreSite"
+
 ##########################################################################
 # Pads/IOs 
 ##########################################################################

openroad/scripts/power_grid.tcl

@@ -29,14 +29,12 @@ if {[info exists power_grid_defined]} {
 ##  Power settings
 ##########################################################################
 # Core Power Ring
-## Space between pads and core -> used for power ring
-set PowRingSpace  35
+## Offset from core to power ring
+set pgcrOffset 2
 ## Spacing must meet TM2 rules
 set pgcrSpacing 6
 ## Width must meet TM2 rules
 set pgcrWidth 10
-## Offset from core to power ring
-set pgcrOffset [expr ($PowRingSpace - $pgcrSpacing - 2 * $pgcrWidth) / 2]
 
 # TopMetal2 Core Power Grid
 set tpg2Width     6; # arbitrary number
@@ -108,7 +106,7 @@ add_pdn_ring -grid {core_grid} \
    -layer        {TopMetal1 TopMetal2} \
    -widths       "$pgcrWidth $pgcrWidth" \
    -spacings     "$pgcrSpacing $pgcrSpacing" \
-   -pad_offsets  "6 6" \
+   -core_offsets "$pgcrOffset $pgcrOffset" \
    -add_connect                        \
    -connect_to_pads                    \
    -connect_to_pad_layers TopMetal2
@@ -135,7 +133,6 @@ add_pdn_connect -grid {core_grid} -layers {TopMetal2 Metal2}
 add_pdn_connect -grid {core_grid} -layers {TopMetal2 Metal4}
 # add_pdn_connect -grid {core_grid} -layers {TopMetal2 TopMetal1}
 # power ring to standard cell rails
-add_pdn_connect -grid {core_grid} -layers {Metal3 Metal1}
 add_pdn_connect -grid {core_grid} -layers {Metal3 Metal2}