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tools: update tool version and cockpitrc (#63)
Tested on ETHZ tardis machines: - LVS clean - 2 metal min-area violations (very small violation, <1% off) - 17 antenna violations (mixed, majority single digit percentages over the ratio) * pdk: update cockpitrc * test: add tc_sram_impl to compile_tech * klayout: improve cockpit tech handling * tools: update to version 2025.07.pre1 * ci: fix pip install on ubuntu-latest * tools: change verilator tracing from vcd to fst FST is a binary format and a lot faster. Additionally, oseda 2025.07 segfaults with vcd tracing only. * openroad: fix final output
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‎.cockpitrc‎

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
[cockpit]
22
# Do not change this section
3-
config = 2025-1
3+
config = 2025-2
44

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# Still Work in Progress
66

@@ -24,6 +24,7 @@
2424
# ixc013g2_iocell_rev1.2.0
2525
# ixc013g2_iocell_rev1.2.1
2626
# open_io_v0.1
27+
# open_io_v0.2
2728
# bondpad : bondpad_70x70_v0
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#
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# STD cell : ixc013g2ng_stdcell_rev0.0.4
@@ -51,15 +52,20 @@
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5253
libs = SG13G2_1.3.1 \
5354
open_stdcell_v3.2 \
54-
open_io_v0.1 \
55+
open_io_v0.2 \
5556
open_sram_v2.1
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# send an e-mail to <[email protected]> to ask for macros. Currently available
5960
# macro datasheets are available under:
6061
# /usr/pack/ihp-sg13-kgf/open_ihp_sg13g2/IHP-Open-PDK-main_v2.0/sg13g2_sram
6162

62-
macros = RM_IHPSG13_1P_256x64_c2_bm_bist
63+
macros = RM_IHPSG13_1P_1024x64_c2_bm_bist \
64+
RM_IHPSG13_1P_2048x64_c2_bm_bist \
65+
RM_IHPSG13_1P_256x48_c2_bm_bist \
66+
RM_IHPSG13_1P_256x64_c2_bm_bist \
67+
RM_IHPSG13_1P_512x64_c2_bm_bist \
68+
RM_IHPSG13_1P_64x64_c2_bm_bist
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[version]
@@ -81,7 +87,7 @@
8187
innovus = innovus-21
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dfii = ic-6
8389
calibre = calibre-2021.3
84-
oseda = oseda -2025.01
90+
oseda = oseda -2025.07
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8692
[command]
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# Startup commands available through the GUI buttons.
@@ -99,8 +105,8 @@
99105
innovus = xterm -g 136x40 -T innovus-21.13 -e "cds_innovus-21.13.000 innovus"
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calibre = xterm -g 120x40 -T calibredrv-2021.3 -e "./start_calibre 2021.3"
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dfii = ./start_dfii
102-
yosys = xterm -g 120x40 -T yosys -e "oseda -2025.01 yosys"
103-
openroad = xterm -g 120x40 -T openroad -e "oseda -2025.01 openroad -gui"
104-
klayout = xterm -g 120x40 -T klayout -e "setenv KLAYOUT_HOME ./.klayout; oseda -2025.01 klayout -e"
108+
yosys = xterm -g 120x40 -T yosys -e "oseda -2025.07 yosys -C"
109+
openroad = xterm -g 120x40 -T openroad -e "oseda -2025.07 openroad -gui"
110+
klayout = xterm -g 120x40 -T klayout -e "setenv KLAYOUT_HOME ./.klayout; oseda -2025.07 klayout -e"
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dz:llama = llama
106112

‎.github/workflows/artistic.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ jobs:
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- name: Install packages in OSEDA
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uses: ./.github/actions/oseda-cmd
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with:
80-
cmd: "pip install gdspy"
80+
cmd: "pip install --break-system-packages gdspy"
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- name: Meercat setup, export top-level GDS
8282
uses: ./.github/actions/oseda-cmd
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with:

‎.github/workflows/short-flow.yml‎

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Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ jobs:
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uses: actions/upload-artifact@v4
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with:
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name: croc-waveform
38-
path: croc.vcd
38+
path: croc.fst
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continue-on-error: true
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4141
- name: Upload simulation output

‎Makefile‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -88,16 +88,21 @@ vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_chip_yosys_debug.v
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8989

9090
# Verilator
91-
VERILATOR_ARGS = --binary -j 0 -Wno-fatal
92-
VERILATOR_ARGS += -Wno-style -Wno-WIDTHEXPAND
93-
VERILATOR_ARGS += --timing --autoflush --trace --trace-structs
91+
# Turn off style warnings and well-defined SystemVerilog warnings that should be part of -Wno-style
92+
VERILATOR_ARGS = -Wno-fatal -Wno-style \
93+
-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
94+
95+
VERILATOR_ARGS += --binary -j 0
96+
VERILATOR_ARGS += --timing --autoflush --trace-fst --trace-threads 2 --trace-structs
9497
VERILATOR_ARGS += --unroll-count 1 --unroll-stmts 1
98+
VERILATOR_ARGS += --x-assign fast --x-initial fast
99+
VERILATOR_CFLAGS += -O3 -march=native -mtune=native
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96101
verilator/croc.f: Bender.lock Bender.yml
97102
$(BENDER) script verilator -t rtl -t verilator -DSYNTHESIS -DVERILATOR > $@
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99104
verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
100-
cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 -CFLAGS "-O1 -march=native" --top tb_croc_soc -f croc.f
105+
cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f
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102107
## Simulate RTL using Verilator
103108
verilator: verilator/obj_dir/Vtb_croc_soc

‎README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ The main SoC configurations are in `rtl/croc_pkg.sv`:
3939
| `BankNumWords` | `512` | Number of 32bit words in a memory bank |
4040
| `NumSramBanks` | `2` | Number of memory banks |
4141

42-
The SRAMs are instantiated via a technology wrapper called `tc_sram` (tc: tech_cells), the technology-independent implementation is in `rtl/tech_cells_generic/tc_sram.sv`. A number of SRAM configurations are implemented using IHP130 SRAM memories in `ihp13/tc_sram.sv`. If an unimplemented SRAM configuration is instantiated it will result in a `tc_sram_blackbox` module which can then be easily identified from the synthesis results.
42+
The SRAMs are instantiated via a technology wrapper called `tc_sram_impl` (tc: tech_cells), the technology-independent implementation is in `rtl/tech_cells_generic/tc_sram_impl.sv`. A number of SRAM configurations are implemented using IHP130 SRAM memories in `ihp13/tc_sram_impl.sv`. If an unimplemented SRAM configuration is instantiated it will result in a `tc_sram_blackbox` module which can then be easily identified from the synthesis results.
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## Bootmodes
4545

‎docker-compose.yml‎

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Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
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services:
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pulp-docker:
10-
image: hpretl/iic-osic-tools:2025.03
10+
image: hpretl/iic-osic-tools:2025.07.pre1
1111
environment:
1212
- UID=${UID}
1313
- GID=${GID}

‎ethz.env‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,9 @@
77
# - Philippe Sauter <[email protected]>
88

99
# used in Makefiles
10-
export BENDER="oseda bender"
11-
export OPENROAD="oseda openroad"
12-
export KLAYOUT="oseda klayout"
13-
export YOSYS="oseda yosys"
14-
export PYTHON3="oseda python3"
15-
export VERILATOR="oseda verilator"
10+
export BENDER="oseda -2025.07 bender"
11+
export OPENROAD="oseda -2025.07 openroad"
12+
export KLAYOUT="oseda -2025.07 klayout"
13+
export YOSYS="oseda -2025.07 yosys"
14+
export PYTHON3="oseda -2025.07 python3"
15+
export VERILATOR="oseda -2025.07 verilator"

‎klayout/def2gds.sh‎

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Original file line numberDiff line numberDiff line change
@@ -11,14 +11,23 @@ cd $klayout_dir
1111
################
1212
### project ###
1313
################
14-
topcell="croc_chip"
15-
defpath="$root_dir/openroad/out/croc.def"
14+
top_design=${TOP_DESIGN:-"croc_chip"}
15+
def_path=${DEF_PATH:-"$root_dir/openroad/out/croc.def"}
1616

1717

1818
################
1919
## technology ##
2020
################
21-
if [[ -f "$root_dir/cockpit.log" ]]; then
21+
tech="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt"
22+
layer="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp"
23+
24+
# create klayout home dir and add pdk to path
25+
export KLAYOUT_HOME="$klayout_dir/.klayout"
26+
export KLAYOUT_PATH="$(realpath $root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout):$KLAYOUT_PATH"
27+
mkdir -p $KLAYOUT_HOME/tech
28+
29+
30+
if [[ -d "$root_dir/technology" ]]; then
2231
echo "Init tech from ETHZ DZ cockpit"
2332
pdk_dir=$(realpath "$root_dir/technology")
2433
pdk_cells_lef_dir="${pdk_dir}/lef"
@@ -52,13 +61,8 @@ gds="$(find "$pdk_cells_gds_dir" -name 'sg13g2_stdcell.gds' -exec realpath {} \;
5261
$(find "$pdk_io_gds_dir" -name 'sg13g2_io.gds' -exec realpath {} \;) \
5362
$(find "$bondpad_gds_dir" -name '*.gds' -exec realpath {} \;)"
5463

55-
tech="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt"
56-
layer="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp"
5764

58-
# create klayout home dir and add pdk to path
59-
export KLAYOUT_HOME="$klayout_dir/.klayout"
60-
export KLAYOUT_PATH="$(realpath $root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout):$KLAYOUT_PATH"
61-
mkdir -p $KLAYOUT_HOME/tech
65+
ln -sfr $klayout_dir/sg13g2.map $KLAYOUT_HOME/tech/sg13g2.map
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6367
# all <lef-files> entries for the tech file
6468
lef_files=""
@@ -68,15 +72,15 @@ done
6872

6973
# replace the placeholder tag with the real lef files
7074
sed "/<lef-files><\/lef-files>/c $lef_files" "$tech" > $KLAYOUT_HOME/tech/sg13g2.lyt
71-
ln -sfr $klayout_dir/sg13g2.map $KLAYOUT_HOME/tech/sg13g2.map
7275

7376
echo "$gds" > $KLAYOUT_HOME/tech/tech_gds.f
7477

78+
7579
klayout_cmd="$KLAYOUT -zz \
76-
-rd design_name=\"$topcell\" \
77-
-rd in_def=\"$defpath\" \
80+
-rd design_name=\"$top_design\" \
81+
-rd in_def=\"$def_path\" \
7882
-rd gds_flist=\"$KLAYOUT_HOME/tech/tech_gds.f\" \
79-
-rd out_file=\"${topcell}.gds\" \
83+
-rd out_file=\"${top_design}.gds\" \
8084
-rd tech_file=\"$KLAYOUT_HOME/tech/sg13g2.lyt\" \
8185
-rd layer_map=\"$KLAYOUT_HOME/tech/sg13g2.map\" \
8286
-rm def2stream.py"

‎openroad/scripts/chip.tcl‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ source scripts/init_tech.tcl
2525

2626
set log_id 0
2727

28+
2829
###############################################################################
2930
# Initialization #
3031
###############################################################################
@@ -291,6 +292,7 @@ report_metrics "${log_id_str}_${proj_name}.grt_repaired"
291292
save_checkpoint ${log_id_str}_${proj_name}.grt_repaired
292293
report_image "${log_id_str}_${proj_name}.grt_repaired" true true false true
293294

295+
294296
###############################################################################
295297
# DETAILED ROUTE #
296298
###############################################################################
@@ -320,6 +322,7 @@ save_checkpoint ${log_id_str}_${proj_name}.drt
320322
report_metrics "${log_id_str}_${proj_name}.drt"
321323
report_image "${log_id_str}_${proj_name}.drt" true false false true
322324

325+
323326
###############################################################################
324327
# FINISHING #
325328
###############################################################################
@@ -335,10 +338,7 @@ global_connect
335338

336339
save_checkpoint ${log_id_str}_${proj_name}.final
337340
report_image "${log_id_str}_${proj_name}.final" true true false true
338-
define_process_corner -ext_model_index 0 X
339-
extract_parasitics -ext_model_file IHP_rcx_patterns.rules
340-
write_spef out/${proj_name}.spef
341-
read_spef out/${proj_name}.spef; # readback parasitics for OpenSTA
341+
estimate_parasitics -global_routing
342342
report_metrics "${log_id_str}_${proj_name}.final"
343343

344344
utl::report "Write output"
@@ -348,4 +348,12 @@ write_verilog out/${proj_name}.v
348348
write_db out/${proj_name}.odb
349349
write_sdc out/${proj_name}.sdc
350350

351+
## WARNING: Currently the extract_parasitics command removes metal patches (eg for min area)
352+
## So if you want to use it, do so at the very end after writing out the def and odb files
353+
# define_process_corner -ext_model_index 0 X
354+
# extract_parasitics -ext_model_file IHP_rcx_patterns.rules
355+
# write_spef out/${proj_name}.spef
356+
# read_spef out/${proj_name}.spef; # readback parasitics for OpenSTA
357+
# report_metrics "${log_id_str}_${proj_name}.extract"
358+
351359
exit

‎openroad/scripts/init_tech.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99

1010
# Initialize the PDK
1111

12-
if {[file exists "../cockpit.log"]} {
12+
if {[file exists "../technology"]} {
1313
utl::report "Init tech from ETHZ DZ cockpit"
1414
set pdk_dir "../technology"
1515
set pdk_cells_lib ${pdk_dir}/lib

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