tools: change verilator tracing from vcd to fst

FST is a binary format and a lot faster.
Additionally, oseda 2025.07 segfaults with vcd tracing only.

Author: phsauter

Makefile

@@ -88,16 +88,21 @@ vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_chip_yosys_debug.v
 
 
 # Verilator
-VERILATOR_ARGS  = --binary -j 0 -Wno-fatal
-VERILATOR_ARGS += -Wno-style -Wno-WIDTHEXPAND
-VERILATOR_ARGS += --timing --autoflush --trace --trace-structs
+# Turn off style warnings and well-defined SystemVerilog warnings that should be part of -Wno-style
+VERILATOR_ARGS = -Wno-fatal -Wno-style \
+	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
+
+VERILATOR_ARGS += --binary -j 0
+VERILATOR_ARGS += --timing --autoflush --trace-fst --trace-threads 2 --trace-structs
 VERILATOR_ARGS +=  --unroll-count 1 --unroll-stmts 1
+VERILATOR_ARGS += --x-assign fast --x-initial fast
+VERILATOR_CFLAGS += -O3 -march=native -mtune=native
 
 verilator/croc.f: Bender.lock Bender.yml
 	$(BENDER) script verilator -t rtl -t verilator -DSYNTHESIS -DVERILATOR > $@
 
 verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
-	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 -CFLAGS "-O1 -march=native" --top tb_croc_soc -f croc.f
+	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f
 
 ## Simulate RTL using Verilator
 verilator: verilator/obj_dir/Vtb_croc_soc

rtl/tb_croc_soc.sv

@@ -441,9 +441,9 @@ module tb_croc_soc #(
 
     initial begin
         $timeformat(-9, 0, "ns", 12); // 1: scale (ns=-9), 2: decimals, 3: suffix, 4: print-field width
-        // configure VCD dump
+        // configure FST (waveform) dump
         `ifdef TRACE_WAVE
-        $dumpfile("croc.vcd");
+        $dumpfile("croc.fst");
         $dumpvars(1,i_croc_soc);
         `endif