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| 1 | +# Copyright (c) 2025 ETH Zurich and University of Bologna. |
| 2 | +# Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | +# SPDX-License-Identifier: Apache-2.0 |
| 4 | +# |
| 5 | +# Authors: |
| 6 | +# - Philippe Sauter <phsauter@iis.ee.ethz.ch> |
| 7 | + |
| 8 | +# A file list given to the yosys-slang frontend to load the design |
| 9 | +# It contains: |
| 10 | +# - include directores expected from SystemVerilog 'include' statements |
| 11 | +# - defines used in some SystemVerilog files |
| 12 | +# often used to guard non-synthesisable code or select some implementation |
| 13 | +# - the paths to all source files |
| 14 | + |
| 15 | ++incdir+rtl/apb/include |
| 16 | ++incdir+rtl/common_cells/include |
| 17 | ++incdir+rtl/cve2/include |
| 18 | ++incdir+rtl/obi/include |
| 19 | ++incdir+rtl/register_interface/include |
| 20 | ++define+TARGET_ASIC |
| 21 | ++define+TARGET_FLIST |
| 22 | ++define+TARGET_IHP13 |
| 23 | ++define+TARGET_RTL |
| 24 | ++define+TARGET_SYNTHESIS |
| 25 | ++define+VERILATOR=1 |
| 26 | ++define+SYNTHESIS=1 |
| 27 | ++define+COMMON_CELLS_ASSERTS_OFF=1 |
| 28 | +rtl/common_cells/binary_to_gray.sv |
| 29 | +rtl/common_cells/cb_filter_pkg.sv |
| 30 | +rtl/common_cells/cc_onehot.sv |
| 31 | +rtl/common_cells/cdc_reset_ctrlr_pkg.sv |
| 32 | +rtl/common_cells/cf_math_pkg.sv |
| 33 | +rtl/common_cells/clk_int_div.sv |
| 34 | +rtl/common_cells/credit_counter.sv |
| 35 | +rtl/common_cells/delta_counter.sv |
| 36 | +rtl/common_cells/ecc_pkg.sv |
| 37 | +rtl/common_cells/edge_propagator_tx.sv |
| 38 | +rtl/common_cells/exp_backoff.sv |
| 39 | +rtl/common_cells/fifo_v3.sv |
| 40 | +rtl/common_cells/gray_to_binary.sv |
| 41 | +rtl/common_cells/isochronous_4phase_handshake.sv |
| 42 | +rtl/common_cells/isochronous_spill_register.sv |
| 43 | +rtl/common_cells/lfsr.sv |
| 44 | +rtl/common_cells/lfsr_16bit.sv |
| 45 | +rtl/common_cells/lfsr_8bit.sv |
| 46 | +rtl/common_cells/lossy_valid_to_stream.sv |
| 47 | +rtl/common_cells/mv_filter.sv |
| 48 | +rtl/common_cells/onehot_to_bin.sv |
| 49 | +rtl/common_cells/plru_tree.sv |
| 50 | +rtl/common_cells/passthrough_stream_fifo.sv |
| 51 | +rtl/common_cells/popcount.sv |
| 52 | +rtl/common_cells/rr_arb_tree.sv |
| 53 | +rtl/common_cells/rstgen_bypass.sv |
| 54 | +rtl/common_cells/serial_deglitch.sv |
| 55 | +rtl/common_cells/shift_reg.sv |
| 56 | +rtl/common_cells/shift_reg_gated.sv |
| 57 | +rtl/common_cells/spill_register_flushable.sv |
| 58 | +rtl/common_cells/stream_demux.sv |
| 59 | +rtl/common_cells/stream_filter.sv |
| 60 | +rtl/common_cells/stream_fork.sv |
| 61 | +rtl/common_cells/stream_intf.sv |
| 62 | +rtl/common_cells/stream_join_dynamic.sv |
| 63 | +rtl/common_cells/stream_mux.sv |
| 64 | +rtl/common_cells/stream_throttle.sv |
| 65 | +rtl/common_cells/sub_per_hash.sv |
| 66 | +rtl/common_cells/sync.sv |
| 67 | +rtl/common_cells/sync_wedge.sv |
| 68 | +rtl/common_cells/unread.sv |
| 69 | +rtl/common_cells/read.sv |
| 70 | +rtl/common_cells/addr_decode_dync.sv |
| 71 | +rtl/common_cells/cdc_2phase.sv |
| 72 | +rtl/common_cells/cdc_4phase.sv |
| 73 | +rtl/common_cells/clk_int_div_static.sv |
| 74 | +rtl/common_cells/addr_decode.sv |
| 75 | +rtl/common_cells/addr_decode_napot.sv |
| 76 | +rtl/common_cells/multiaddr_decode.sv |
| 77 | +rtl/common_cells/cb_filter.sv |
| 78 | +rtl/common_cells/cdc_fifo_2phase.sv |
| 79 | +rtl/common_cells/clk_mux_glitch_free.sv |
| 80 | +rtl/common_cells/counter.sv |
| 81 | +rtl/common_cells/ecc_decode.sv |
| 82 | +rtl/common_cells/ecc_encode.sv |
| 83 | +rtl/common_cells/edge_detect.sv |
| 84 | +rtl/common_cells/lzc.sv |
| 85 | +rtl/common_cells/max_counter.sv |
| 86 | +rtl/common_cells/rstgen.sv |
| 87 | +rtl/common_cells/spill_register.sv |
| 88 | +rtl/common_cells/stream_delay.sv |
| 89 | +rtl/common_cells/stream_fifo.sv |
| 90 | +rtl/common_cells/stream_fork_dynamic.sv |
| 91 | +rtl/common_cells/stream_join.sv |
| 92 | +rtl/common_cells/cdc_reset_ctrlr.sv |
| 93 | +rtl/common_cells/cdc_fifo_gray.sv |
| 94 | +rtl/common_cells/fall_through_register.sv |
| 95 | +rtl/common_cells/id_queue.sv |
| 96 | +rtl/common_cells/stream_to_mem.sv |
| 97 | +rtl/common_cells/stream_arbiter_flushable.sv |
| 98 | +rtl/common_cells/stream_fifo_optimal_wrap.sv |
| 99 | +rtl/common_cells/stream_register.sv |
| 100 | +rtl/common_cells/stream_xbar.sv |
| 101 | +rtl/common_cells/cdc_fifo_gray_clearable.sv |
| 102 | +rtl/common_cells/cdc_2phase_clearable.sv |
| 103 | +rtl/common_cells/mem_to_banks_detailed.sv |
| 104 | +rtl/common_cells/stream_arbiter.sv |
| 105 | +rtl/common_cells/stream_omega_net.sv |
| 106 | +rtl/common_cells/mem_to_banks.sv |
| 107 | +rtl/apb/apb_pkg.sv |
| 108 | +rtl/register_interface/reg_intf.sv |
| 109 | +rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv |
| 110 | +rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv |
| 111 | +rtl/register_interface/periph_to_reg.sv |
| 112 | +rtl/register_interface/reg_to_apb.sv |
| 113 | +rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv |
| 114 | +rtl/register_interface/lowrisc_opentitan/prim_subreg.sv |
| 115 | +rtl/apb_uart/slib_clock_div.sv |
| 116 | +rtl/apb_uart/slib_counter.sv |
| 117 | +rtl/apb_uart/slib_edge_detect.sv |
| 118 | +rtl/apb_uart/slib_fifo.sv |
| 119 | +rtl/apb_uart/slib_input_filter.sv |
| 120 | +rtl/apb_uart/slib_input_sync.sv |
| 121 | +rtl/apb_uart/slib_mv_filter.sv |
| 122 | +rtl/apb_uart/uart_baudgen.sv |
| 123 | +rtl/apb_uart/uart_interrupt.sv |
| 124 | +rtl/apb_uart/uart_receiver.sv |
| 125 | +rtl/apb_uart/uart_transmitter.sv |
| 126 | +rtl/apb_uart/apb_uart.sv |
| 127 | +rtl/apb_uart/apb_uart_wrap.sv |
| 128 | +rtl/apb_uart/reg_uart_wrap.sv |
| 129 | +rtl/cve2/cve2_pkg.sv |
| 130 | +rtl/cve2/cve2_alu.sv |
| 131 | +rtl/cve2/cve2_compressed_decoder.sv |
| 132 | +rtl/cve2/cve2_controller.sv |
| 133 | +rtl/cve2/cve2_counter.sv |
| 134 | +rtl/cve2/cve2_csr.sv |
| 135 | +rtl/cve2/cve2_decoder.sv |
| 136 | +rtl/cve2/cve2_fetch_fifo.sv |
| 137 | +rtl/cve2/cve2_load_store_unit.sv |
| 138 | +rtl/cve2/cve2_multdiv_fast.sv |
| 139 | +rtl/cve2/cve2_multdiv_slow.sv |
| 140 | +rtl/cve2/cve2_pmp.sv |
| 141 | +rtl/cve2/cve2_register_file_ff.sv |
| 142 | +rtl/cve2/cve2_wb.sv |
| 143 | +rtl/cve2/cve2_cs_registers.sv |
| 144 | +rtl/cve2/cve2_ex_block.sv |
| 145 | +rtl/cve2/cve2_id_stage.sv |
| 146 | +rtl/cve2/cve2_prefetch_buffer.sv |
| 147 | +rtl/cve2/cve2_if_stage.sv |
| 148 | +rtl/cve2/cve2_core.sv |
| 149 | +rtl/obi/obi_pkg.sv |
| 150 | +rtl/obi/obi_intf.sv |
| 151 | +rtl/obi/obi_rready_converter.sv |
| 152 | +rtl/obi/obi_atop_resolver.sv |
| 153 | +rtl/obi/obi_demux.sv |
| 154 | +rtl/obi/obi_err_sbr.sv |
| 155 | +rtl/obi/obi_mux.sv |
| 156 | +rtl/obi/obi_sram_shim.sv |
| 157 | +rtl/obi/obi_xbar.sv |
| 158 | +rtl/riscv-dbg/dm_pkg.sv |
| 159 | +rtl/riscv-dbg/debug_rom/debug_rom.sv |
| 160 | +rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv |
| 161 | +rtl/riscv-dbg/dm_csrs.sv |
| 162 | +rtl/riscv-dbg/dm_mem.sv |
| 163 | +rtl/riscv-dbg/dmi_cdc.sv |
| 164 | +rtl/riscv-dbg/dmi_jtag_tap.sv |
| 165 | +rtl/riscv-dbg/dm_sba.sv |
| 166 | +rtl/riscv-dbg/dm_top.sv |
| 167 | +rtl/riscv-dbg/dmi_jtag.sv |
| 168 | +rtl/riscv-dbg/dm_obi_top.sv |
| 169 | +rtl/timer_unit/timer_unit_counter.sv |
| 170 | +rtl/timer_unit/timer_unit_counter_presc.sv |
| 171 | +rtl/timer_unit/apb_timer_unit.sv |
| 172 | +rtl/timer_unit/timer_unit.sv |
| 173 | +ihp13/tc_clk.sv |
| 174 | +ihp13/tc_sram.sv |
| 175 | +rtl/croc_pkg.sv |
| 176 | +rtl/user_pkg.sv |
| 177 | +rtl/soc_ctrl/soc_ctrl_reg_pkg.sv |
| 178 | +rtl/gpio/gpio_reg_pkg.sv |
| 179 | +rtl/core_wrap.sv |
| 180 | +rtl/soc_ctrl/soc_ctrl_reg_top.sv |
| 181 | +rtl/gpio/gpio_reg_top.sv |
| 182 | +rtl/gpio/gpio.sv |
| 183 | +rtl/croc_domain.sv |
| 184 | +rtl/user_domain.sv |
| 185 | +rtl/croc_soc.sv |
| 186 | +rtl/croc_chip.sv |
| 187 | + |
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