bender: update IPs, remove register_interface

Author: phsauter

Bender.local

@@ -3,7 +3,6 @@ overrides:
   tech_cells_generic: { path: "rtl/tech_cells_generic" }
   common_cells: { path: "rtl/common_cells" }
   apb: { path: "rtl/apb" }
-  register_interface: { path: "rtl/register_interface" }
   obi_peripherals: { path: "rtl/obi_uart" }
   ibex: { path: "rtl/ibex" }
   obi: { path: "rtl/obi" }

Bender.lock

@@ -42,15 +42,6 @@ packages:
     dependencies:
     - common_cells
     - obi
-  register_interface:
-    revision: null
-    version: null
-    source:
-      Path: rtl/register_interface
-    dependencies:
-    - apb
-    - common_cells
-    - common_verification
   riscv-dbg:
     revision: null
     version: null

Bender.yml

@@ -9,13 +9,12 @@ package:
 
 dependencies:
   # IMPORTANT: see vendor_package at the bottom
-  common_cells:         { git: "https://github.com/pulp-platform/common_cells.git",         version: 1.37.0 }
-  common_verification:  { git: "https://github.com/pulp-platform/common_verification.git",  version: 0.2.5  }
+  common_cells:         { git: "https://github.com/pulp-platform/common_cells.git",         version: 1.39.0 }
+  common_verification:  { git: "https://github.com/pulp-platform/common_verification.git",  rev: 5fd30c1    } # 0.2.5+
   riscv-dbg:            { git: "https://github.com/pulp-platform/riscv-dbg.git",            rev: "verilator-phsauter" }
-  tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git",   version: 0.2.13 }
-  register_interface:   { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.1  }
+  tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git",   rev: fca524a    } # 0.2.13+
   apb:                  { git: "https://github.com/pulp-platform/apb.git",                  version: 0.2.4  }
-  obi:                  { git: "https://github.com/pulp-platform/obi.git",                  version: 0.1.7  }
+  obi:                  { git: "https://github.com/pulp-platform/obi.git",                  rev: 6a724da    } # 0.1.7+
   obi_peripherals:      { git: "https://github.com/pulp-platform/obi_peripherals.git",      rev: 21ee04d    } # UART
   cve2:                 { path: "rtl/cve2" } # a vendor package (no Bender.yml), see below 
 
@@ -77,8 +76,8 @@ vendor_package:
   #################################
   - name: common_cells
     target_dir: rtl/common_cells
-    upstream: { git: "https://github.com/pulp-platform/common_cells.git", rev: "9afda9abb565971649c2aa0985639c096f351171" } # v1.38.0
-    patch_dir: "rtl/patches/common_cells"
+    upstream: { git: "https://github.com/pulp-platform/common_cells.git", rev: "9ca8a7655f741e7dd5736669a20a301325194c28" } # v1.39.0
+    patch_dir: "rtl/.patches/common_cells"
     exclude_from_upstream:
       - "src/deprecated"
     mapping:
@@ -89,16 +88,16 @@ vendor_package:
 
   - name: common_verification
     target_dir: rtl/common_verification
-    upstream: { git: "https://github.com/pulp-platform/common_verification.git", rev: "fb1885f48ea46164a10568aeff51884389f67ae3" } # branch verilator-fix
-    patch_dir: "rtl/patches/common_verification"
+    upstream: { git: "https://github.com/pulp-platform/common_verification.git", rev: "5fd30c18a6be6f664d1ef9e44d04956fb4e3364e" } # newest (0.2.5+)
+    patch_dir: "rtl/.patches/common_verification"
     mapping:
       - { from: 'src/clk_rst_gen.sv', to: 'clk_rst_gen.sv', patch_dir: 'src/' }
       - { from: 'Bender.yml',         to: 'Bender.yml',     patch_dir: '' }
 
   - name: tech_cells_generic
     target_dir: rtl/tech_cells_generic
-    upstream: { git: "https://github.com/pulp-platform/tech_cells_generic.git", rev: "7968dd6e6180df2c644636bc6d2908a49f2190cf" } # v0.2.13
-    patch_dir: "rtl/patches/tech_cells_generic"
+    upstream: { git: "https://github.com/pulp-platform/tech_cells_generic.git", rev: "fca524a1174f6363ba0e778f37b9f398257d4b8f" } # newest (v0.2.13+)
+    patch_dir: "rtl/.patches/tech_cells_generic"
     mapping:
       - { from: 'src/rtl/',   to: '',           patch_dir: 'rtl/' }
       - { from: 'src/fpga/',  to: 'fpga/',      patch_dir: 'fpga/' }
@@ -111,8 +110,8 @@ vendor_package:
   #############################
   - name: obi
     target_dir: rtl/obi
-    upstream: { git: "https://github.com/pulp-platform/obi.git", rev: "ad1d48f025be540344960ea83b4bff39876f9b36" } # newest as of writing (0.1.6+)
-    patch_dir: "rtl/patches/obi"
+    upstream: { git: "https://github.com/pulp-platform/obi.git", rev: "6a724da5c8d6412b88b6948746e04c1adf39d017" } # newest (0.1.7+)
+    patch_dir: "rtl/.patches/obi"
     exclude_from_upstream:
       - "src/test"
     mapping:
@@ -121,23 +120,10 @@ vendor_package:
       - { from: 'Bender.yml',  to: 'Bender.yml',  patch_dir: '' }
       - { from: 'Readme.md',   to: 'Readme.md',   patch_dir: '' }
 
-  - name: register_interface
-    target_dir: rtl/register_interface
-    upstream: { git: "https://github.com/pulp-platform/register_interface.git", rev: "3b2bf592100b769977c76e51812c55cd742882f6" } # v0.4.1
-    patch_dir: "rtl/patches/register_interface"
-    mapping:
-      - { from: 'src/periph_to_reg.sv',         to: 'periph_to_reg.sv',            patch_dir: 'src/' }
-      - { from: 'src/reg_intf.sv',              to: 'reg_intf.sv',                 patch_dir: 'src/' }
-      - { from: 'src/reg_to_apb.sv',            to: 'reg_to_apb.sv',               patch_dir: 'src/' }
-      - { from: 'include/register_interface/',  to: 'include/register_interface/', patch_dir: 'include/' }
-      - { from: 'vendor/lowrisc_opentitan/src', to: 'lowrisc_opentitan',           patch_dir: 'vendor/' }
-      - { from: 'Bender.yml',                   to: 'Bender.yml',                  patch_dir: '' }
-      - { from: 'README.md',                    to: 'README.md',                   patch_dir: '' }
-
   - name: apb
     target_dir: rtl/apb
     upstream: { git: "https://github.com/pulp-platform/apb.git", rev: "77ddf073f194d44b9119949d2421be59789e69ae" } # v0.2.4
-    patch_dir: "rtl/patches/apb"
+    patch_dir: "rtl/.patches/apb"
     mapping:
       - { from: 'src/apb_pkg.sv', to: 'apb_pkg.sv',   patch_dir: 'src/' }
       - { from: 'include/apb/',   to: 'include/apb/', patch_dir: 'include/' }
@@ -150,8 +136,8 @@ vendor_package:
   ###############
   - name: riscv-dbg
     target_dir: rtl/riscv-dbg
-    upstream: { git: "https://github.com/pulp-platform/riscv-dbg.git", rev: "a21b39ad11833d9afc7ab366944b811d5a641901" } # branch verilator-phsauter
-    patch_dir: "rtl/patches/riscv-dbg"
+    upstream: { git: "https://github.com/pulp-platform/riscv-dbg.git", rev: "13835b1d45f013a0760ecebd744fee6cf2e3b96a" } # branch verilator-phsauter
+    patch_dir: "rtl/.patches/riscv-dbg"
     mapping:
       - { from: 'src/',                               to: '',                                   patch_dir: 'src/' }
       - { from: 'debug_rom/debug_rom.sv',             to: 'debug_rom/debug_rom.sv',             patch_dir: 'debug_rom/' }
@@ -164,7 +150,7 @@ vendor_package:
   - name: obi_peripherals
     target_dir: rtl/obi_uart
     upstream: { git: "https://github.com/pulp-platform/obi_peripherals.git", rev: "21ee04d267025f6ea3d2faa462272287ddcb9bbb"  } # newest
-    patch_dir: "rtl/patches/obi_uart"
+    patch_dir: "rtl/.patches/obi_uart"
     mapping:
       - { from: 'hw/obi_uart/', to: '',            patch_dir: 'hw/' }
       - { from: 'Bender.yml',   to: 'Bender.yml',  patch_dir: '' }
@@ -173,13 +159,13 @@ vendor_package:
   #########
   # core  #
   #########
-  # CVE2/Ibex
+  # CVE2
   - name: cve2
     target_dir: rtl/cve2
-    upstream: { git: "https://github.com/openhwgroup/cve2.git", rev: "370793f52488d1022d0554d194ad24f125156acc" }
-    patch_dir: "rtl/patches/cve2"
+    upstream: { git: "https://github.com/openhwgroup/cve2.git", rev: "53076d64c97685b1d2f5d07cd7f5cc439cf1f351" } # newest
+    patch_dir: "rtl/.patches/cve2"
     mapping:
-      - { from: 'rtl/',                                         to: '',                      patch_dir: 'rtl/' }
-      - { from: 'README.md',                                    to: 'README.md',             patch_dir: '' }
-      - { from: 'doc/03_reference/images/blockdiagram.svg',     to: 'blockdiagram.svg',      patch_dir: '' }
-      - { from: 'vendor/lowrisc_ip/ip/prim/rtl/',               to: 'include/lowrisc_prim/', patch_dir: 'lowrisc_prim/' }
+      - { from: 'rtl/',                                            to: '',                      patch_dir: 'rtl/' }
+      - { from: 'README.md',                                       to: 'README.md',             patch_dir: '' }
+      - { from: 'doc/03_reference/images/blockdiagram.drawio.svg', to: 'blockdiagram.svg',      patch_dir: '' }
+      - { from: 'vendor/lowrisc_ip/ip/prim/rtl/',                  to: 'include/lowrisc_prim/', patch_dir: 'lowrisc_prim/' }

Makefile

@@ -13,7 +13,6 @@ YOSYS     ?= yosys
 OPENROAD  ?= openroad
 KLAYOUT   ?= klayout
 VSIM      ?= vsim
-REGGEN    ?= $(PYTHON3) $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
 
 # Directories
 # directory of the path to the last called Makefile (this one)

croc.flist

@@ -2,7 +2,6 @@
 +incdir+rtl/common_cells/include
 +incdir+rtl/cve2/include
 +incdir+rtl/obi/include
-+incdir+rtl/register_interface/include
 +define+TARGET_ASIC
 +define+TARGET_FLIST
 +define+TARGET_IHP13
@@ -24,6 +23,7 @@ rtl/common_cells/edge_propagator_tx.sv
 rtl/common_cells/exp_backoff.sv
 rtl/common_cells/fifo_v3.sv
 rtl/common_cells/gray_to_binary.sv
+rtl/common_cells/heaviside.sv
 rtl/common_cells/isochronous_4phase_handshake.sv
 rtl/common_cells/isochronous_spill_register.sv
 rtl/common_cells/lfsr.sv
@@ -35,6 +35,7 @@ rtl/common_cells/onehot_to_bin.sv
 rtl/common_cells/plru_tree.sv
 rtl/common_cells/passthrough_stream_fifo.sv
 rtl/common_cells/popcount.sv
+rtl/common_cells/ring_buffer.sv
 rtl/common_cells/rr_arb_tree.sv
 rtl/common_cells/rstgen_bypass.sv
 rtl/common_cells/serial_deglitch.sv
@@ -54,9 +55,11 @@ rtl/common_cells/sync_wedge.sv
 rtl/common_cells/unread.sv
 rtl/common_cells/read.sv
 rtl/common_cells/addr_decode_dync.sv
+rtl/common_cells/boxcar.sv
 rtl/common_cells/cdc_2phase.sv
 rtl/common_cells/cdc_4phase.sv
 rtl/common_cells/clk_int_div_static.sv
+rtl/common_cells/trip_counter.sv
 rtl/common_cells/addr_decode.sv
 rtl/common_cells/addr_decode_napot.sv
 rtl/common_cells/multiaddr_decode.sv
@@ -90,19 +93,22 @@ rtl/common_cells/mem_to_banks_detailed.sv
 rtl/common_cells/stream_arbiter.sv
 rtl/common_cells/stream_omega_net.sv
 rtl/common_cells/mem_to_banks.sv
-rtl/apb/apb_pkg.sv
 rtl/obi/obi_pkg.sv
 rtl/obi/obi_intf.sv
 rtl/obi/obi_rready_converter.sv
+rtl/obi/apb_to_obi.sv
+rtl/obi/obi_to_apb.sv
 rtl/obi/obi_atop_resolver.sv
 rtl/obi/obi_cut.sv
 rtl/obi/obi_demux.sv
 rtl/obi/obi_err_sbr.sv
 rtl/obi/obi_mux.sv
 rtl/obi/obi_sram_shim.sv
 rtl/obi/obi_xbar.sv
+rtl/apb/apb_pkg.sv
 rtl/cve2/cve2_pkg.sv
 rtl/cve2/cve2_alu.sv
+rtl/cve2/cve2_branch_predict.sv
 rtl/cve2/cve2_compressed_decoder.sv
 rtl/cve2/cve2_controller.sv
 rtl/cve2/cve2_counter.sv
@@ -129,15 +135,6 @@ rtl/obi_uart/obi_uart_rx.sv
 rtl/obi_uart/obi_uart_tx.sv
 rtl/obi_uart/obi_uart_register.sv
 rtl/obi_uart/obi_uart.sv
-rtl/obi_timer/obi_timer_reg_pkg.sv
-rtl/obi_timer/obi_timer.sv
-rtl/register_interface/reg_intf.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv
-rtl/register_interface/periph_to_reg.sv
-rtl/register_interface/reg_to_apb.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg.sv
 rtl/riscv-dbg/dm_pkg.sv
 rtl/riscv-dbg/debug_rom/debug_rom.sv
 rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv
@@ -149,20 +146,21 @@ rtl/riscv-dbg/dm_sba.sv
 rtl/riscv-dbg/dm_top.sv
 rtl/riscv-dbg/dmi_jtag.sv
 rtl/riscv-dbg/dm_obi_top.sv
-rtl/clint/clint_reg_pkg.sv
-rtl/clint/clint.sv
 ihp13/tc_clk.sv
 ihp13/tc_sram_impl.sv
 rtl/croc_pkg.sv
 rtl/user_pkg.sv
 rtl/soc_ctrl/soc_ctrl_regs_pkg.sv
 rtl/gpio/gpio_reg_pkg.sv
+rtl/clint/clint_reg_pkg.sv
+rtl/obi_timer/obi_timer_reg_pkg.sv
 rtl/core_wrap.sv
 rtl/soc_ctrl/soc_ctrl_regs.sv
 rtl/gpio/gpio_reg_top.sv
 rtl/gpio/gpio.sv
+rtl/clint/clint.sv
+rtl/obi_timer/obi_timer.sv
 rtl/croc_domain.sv
 rtl/user_domain.sv
 rtl/croc_soc.sv
 rtl/croc_chip.sv
-

…pb/0001-adjust-Bender-source-paths.patch …pb/0001-adjust-Bender-source-paths.patchrtl/patches/apb/0001-adjust-Bender-source-paths.patch renamed to rtl/.patches/apb/0001-adjust-Bender-source-paths.patch rtl/patches/apb/0001-adjust-Bender-source-paths.patch renamed to rtl/.patches/apb/0001-adjust-Bender-source-paths.patch

@@ -1,17 +1,17 @@
-From 75a75826ae9701bc5bcfce7399a80f435786c7c8 Mon Sep 17 00:00:00 2001
+From 7775101e0ab8668f8abe1d7b0854ae13a153b6da Mon Sep 17 00:00:00 2001
 From: Philippe Sauter <phsauter@iis.ee.ethz.ch>
-Date: Tue, 6 May 2025 17:16:23 +0200
+Date: Fri, 19 Dec 2025 15:40:35 +0100
 Subject: [PATCH] adjust Bender source paths
 
 ---
- Bender.yml | 223 +++++++++++++++++++----------------------------------
- 1 file changed, 79 insertions(+), 144 deletions(-)
+ Bender.yml | 231 +++++++++++++++++++----------------------------------
+ 1 file changed, 83 insertions(+), 148 deletions(-)
 
 diff --git a/Bender.yml b/Bender.yml
-index df66670..208fc3b 100644
+index cf837d6..14c2e46 100644
 --- a/Bender.yml
 +++ b/Bender.yml
-@@ -23,157 +23,92 @@ sources:
+@@ -23,161 +23,96 @@ sources:
    # etc. Files within a level are ordered alphabetically.
 
    # Level 0
@@ -32,6 +32,7 @@ index df66670..208fc3b 100644
 -      - src/exp_backoff.sv
 -      - src/fifo_v3.sv
 -      - src/gray_to_binary.sv
+-      - src/heaviside.sv
 -      - src/isochronous_4phase_handshake.sv
 -      - src/isochronous_spill_register.sv
 -      - src/lfsr.sv
@@ -43,6 +44,7 @@ index df66670..208fc3b 100644
 -      - src/plru_tree.sv
 -      - src/passthrough_stream_fifo.sv
 -      - src/popcount.sv
+-      - src/ring_buffer.sv
 -      - src/rr_arb_tree.sv
 -      - src/rstgen_bypass.sv
 -      - src/serial_deglitch.sv
@@ -73,6 +75,7 @@ index df66670..208fc3b 100644
 +      - exp_backoff.sv
 +      - fifo_v3.sv
 +      - gray_to_binary.sv
++      - heaviside.sv
 +      - isochronous_4phase_handshake.sv
 +      - isochronous_spill_register.sv
 +      - lfsr.sv
@@ -84,6 +87,7 @@ index df66670..208fc3b 100644
 +      - plru_tree.sv
 +      - passthrough_stream_fifo.sv
 +      - popcount.sv
++      - ring_buffer.sv
 +      - rr_arb_tree.sv
 +      - rstgen_bypass.sv
 +      - serial_deglitch.sv
@@ -104,13 +108,17 @@ index df66670..208fc3b 100644
 +      - read.sv
        # Level 1
 -      - src/addr_decode_dync.sv
+-      - src/boxcar.sv
 -      - src/cdc_2phase.sv
 -      - src/cdc_4phase.sv
 -      - src/clk_int_div_static.sv
+-      - src/trip_counter.sv
 +      - addr_decode_dync.sv
++      - boxcar.sv
 +      - cdc_2phase.sv
 +      - cdc_4phase.sv
 +      - clk_int_div_static.sv
++      - trip_counter.sv
        # Level 2
 -      - src/addr_decode.sv
 -      - src/addr_decode_napot.sv
@@ -249,5 +257,5 @@ index df66670..208fc3b 100644
 -  - src/edge_propagator_rx.sv
 +      - mem_to_banks.sv
 -- 
-2.39.3
+2.43.5
 

…ls/0001-adjust-Bender-source-paths.patch …ls/0001-adjust-Bender-source-paths.patchrtl/patches/common_cells/0001-adjust-Bender-source-paths.patch renamed to rtl/.patches/common_cells/0001-adjust-Bender-source-paths.patch rtl/patches/common_cells/0001-adjust-Bender-source-paths.patch renamed to rtl/.patches/common_cells/0001-adjust-Bender-source-paths.patch

@@ -1,25 +1,25 @@
-From b29bab50d89f40c5523d99012396d8c0e7433896 Mon Sep 17 00:00:00 2001
+From e0024cc29343389ac8f96dee80babcf2a14d1e77 Mon Sep 17 00:00:00 2001
 From: Philippe Sauter <phsauter@iis.ee.ethz.ch>
-Date: Tue, 19 Nov 2024 14:43:00 +0100
-Subject: [PATCH] adjust-blockdiagram-path
+Date: Fri, 19 Dec 2025 17:21:19 +0100
+Subject: [PATCH] tmp
 
 ---
  README.md | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/README.md b/README.md
-index 23d220fa..d750c868 100644
+index e23270ea..3415de97 100644
 --- a/README.md
 +++ b/README.md
 @@ -16,7 +16,7 @@ Integer Multiplication and Division (M), and Compressed (C) extensions.
  The block diagram below shows the *small* parametrization with a 2-stage
  pipeline.
 
--<p align="center"><img src="doc/03_reference/images/blockdiagram.svg" width="650"></p>
+-<p align="center"><img src="doc/03_reference/images/blockdiagram.drawio.svg" width="650"></p>
 +<p align="center"><img src="blockdiagram.svg" width="650"></p>
 
  CV32E20 was initially developed as part of the [PULP platform](https://www.pulp-platform.org)
  under the name [&#34;Zero-riscy&#34;](https://doi.org/10.1109/PATMOS.2017.8106976), and has been
 -- 
-2.34.1
+2.43.5
 

…on/0001-adjust-Bender-source-paths.patch …on/0001-adjust-Bender-source-paths.patchrtl/patches/common_verification/0001-adjust-Bender-source-paths.patch renamed to rtl/.patches/common_verification/0001-adjust-Bender-source-paths.patch rtl/patches/common_verification/0001-adjust-Bender-source-paths.patch renamed to rtl/.patches/common_verification/0001-adjust-Bender-source-paths.patch

@@ -1,6 +1,6 @@
-From 32df3d3c21d4b96aec4fff64ae11fb539be445dd Mon Sep 17 00:00:00 2001
+From 155dc29c1933aafbe67b589571436062b8b4b4c3 Mon Sep 17 00:00:00 2001
 From: Philippe Sauter <phsauter@iis.ee.ethz.ch>
-Date: Tue, 19 Nov 2024 16:15:45 +0100
+Date: Fri, 19 Dec 2025 16:20:07 +0100
 Subject: [PATCH] remove unused files
 
 ---
@@ -17851,5 +17851,5 @@ index 39307e5a..00000000
 -
 -endmodule
 -- 
-2.34.1
+2.43.5