yosys: refactor, simplify and comment

Author: phsauter

Makefile

@@ -74,7 +74,7 @@ vsim: vsim/compile_rtl.tcl $(SW_HEX)
 	cd vsim; $(VSIM) +binary="$(realpath $(SW_HEX))" -gui tb_croc_soc $(VSIM_ARGS)
 
 ## Simulate netlist using Questasim/Modelsim/vsim
-vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_yosys_debug.v
+vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_chip_yosys_debug.v
 	rm -rf vsim/work
 	cd vsim; $(VSIM) -c -do "source compile_netlist.tcl; source compile_tech.tcl; exit"
 	cd vsim; $(VSIM) -gui tb_croc_soc $(VSIM_ARGS)
@@ -101,12 +101,11 @@ verilator: verilator/obj_dir/Vtb_croc_soc
 ####################
 # Open Source Flow #
 ####################
+# Bender manages the different IPs and can be used to generate file-lists for synthesis
 TOP_DESIGN     ?= croc_chip
 DUT_DESIGN	   ?= croc_soc
 BENDER_TARGETS ?= asic ihp13 rtl synthesis
 SV_DEFINES     ?= VERILATOR SYNTHESIS COMMON_CELLS_ASSERTS_OFF
-PICKLE_OUT	   ?= $(PROJ_DIR)/pickle
-SV_FLIST       ?= $(PROJ_DIR)/croc.flist
 
 ## Generate croc.flist used to read design in yosys
 yosys-flist: Bender.lock Bender.yml rtl/*/Bender.yml

yosys/project-synth.mk

@@ -14,7 +14,7 @@ print_stats
 # strash can fix some yosys-convertion edge-cases, good idea to run first
 strash
 
-rec_start3 {REC_AIG}
+rec_start3 src/lazy_man_synth_library.aig
 
 # main optimization iteration:
 alias &opt_iter "&st; &if -y -K 6; &syn2; &if -K 6; &st; &b"

yosys/scripts/abc-opt.script

@@ -5,28 +5,26 @@
 # Authors:
 # - Philippe Sauter <phsauter@iis.ee.ethz.ch>
 
-# get environment variables
-set yosys_dir [file dirname [file dirname [info script]]]
-set root_dir [file dirname $yosys_dir]
+# All paths relative to yosys/
 
-if {[file exists "$root_dir/cockpit.log"]} {
+if {[file exists "../technology"]} {
 	puts "0. Executing init_tech: load technology from ETHZ DZ cockpit"
-	set pdk_dir "$root_dir/technology"
+	set pdk_dir "../technology"
 	set pdk_cells_lib ${pdk_dir}/lib
 	set pdk_sram_lib  ${pdk_dir}/lib
 	set pdk_io_lib    ${pdk_dir}/lib
 } else {
 	puts "0. Executing init_tech: load technology from Github PDK"
 	if {![info exists pdk_dir]} {
-		set pdk_dir "$root_dir/ihp13/pdk"
+		set pdk_dir "../ihp13/pdk"
 	}
 	set pdk_cells_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib
 	set pdk_sram_lib  ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_sram/lib
 	set pdk_io_lib    ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_io/lib
 }
 
 set tech_cells [list "$pdk_cells_lib/sg13g2_stdcell_typ_1p20V_25C.lib"]
-set tech_macros [glob -nocomplain -directory $pdk_sram_lib *_typ_1p20V_25C.lib]
+set tech_macros [glob -directory $pdk_sram_lib *_typ_1p20V_25C.lib]
 lappend tech_macros "$pdk_io_lib/sg13g2_io_typ_1p2V_3p3V_25C.lib"
 
 # for hilomap

yosys/scripts/init_tech.tcl

@@ -5,41 +5,22 @@
 # Authors:
 # - Philippe Sauter <phsauter@iis.ee.ethz.ch>
 
-# Common setup used for all yosys scripts
+# Preparation for the synthesis flow
+# A common setup to provide some functionality and define variables
 
 # list of global variables that may be used
+# define with scheme: <local-var> { <ENVVAR>  <fallback> }
 set variables {
-    vlog_files  { VLOG_FILES               ""                       }
-    sv_flist    { SV_FLIST                 ""                       }
-    top_design  { TOP_DESIGN               ""                       }
-    hier_depth  { HIER_DEPTH               0                        }
-    period_ps   { YOSYS_TARGET_PERIOD_PS   5000                     }
-    proj_name   { PROJ_NAME                ""                       }
-    build_dir   { BUILD                    "[set dir [pwd]]/out"    }
-    work_dir    { WORK                     "[set dir [pwd]]/WORK"   }
-    report_dir  { REPORTS                  "[set dir [pwd]]/report" }
-    netlist     { NETLIST                  ""                       }
+    sv_flist    { SV_FLIST    "../croc.flist" }
+    top_design  { TOP_DESIGN  "croc_chip"     }
+    period_ps   { PERIOD_PS   10000           }
+    out_dir     { OUT         out             }
+    tmp_dir     { TMP         tmp             }
+    rep_dir     { REPORTS     reports         }
 }
 
-# either use env-var or default to fallback
-foreach var [dict keys $variables] {  
-    set values [dict get $variables $var]
-    set env_var [lindex $values 0]
-    set fallback [lindex $values 1]
-
-    if {[info exists ::env($env_var)]} {
-        puts "using: $var= '$::env($env_var)'"
-        set $var $::env($env_var)
-    } else {
-        puts "using: '$var= $fallback'"
-        set $var $fallback
-    }
-}
-
-if {[string eq $netlist ""]} {
-    set netlist ${build_dir}/${top_design}_netlist.v
-}
 
+# check if an env-var exists and is non-empty
 proc envVarValid {var_name} {
     if { [info exists ::env($var_name)]} {
 	    if {$::env($var_name) != "0" && $::env($var_name) ne ""} {
@@ -49,14 +30,26 @@ proc envVarValid {var_name} {
     return 0
 }
 
+# If the ENVVAR is valid use it, otherwise use fallback
+foreach var [dict keys $variables] {  
+    set values [dict get $variables $var]
+    set env_var [lindex $values 0]
+    set fallback [lindex $values 1]
+
+    if {[envVarValid $env_var]} {
+        puts "using: $var= '$::env($env_var)'"
+        set $var $::env($env_var)
+    }
+}
+
+# process ABC script and write to temporary directory
 proc processAbcScript {abc_script} {
-    global work_dir period_ps
+    global tmp_dir
     set src_dir [file join [file dirname [info script]] ../src]
-    set abc_out_path $work_dir/[file tail $abc_script]
+    set abc_out_path $tmp_dir/[file tail $abc_script]
 
     set raw [read -nonewline [open $abc_script r]]
-    set abc_script_delay [string map -nocase [list "{D}" [subst "-D $period_ps"]] $raw]
-    set abc_script_recaig [string map -nocase [list "{REC_AIG}" [subst "$src_dir/rec6Lib_final_filtered3_recanon_basilisk.aig"]] $abc_script_delay]
+    set abc_script_recaig [string map -nocase [list "{REC_AIG}" [subst "$src_dir/lazy_man_synth_library.aig"]] $raw]
     set abc_out [open $abc_out_path w]
     puts -nonewline $abc_out $abc_script_recaig