hw: add wfi trampoline bootrom

Author: phsauter

.github/scripts/check_sim.sh

@@ -8,7 +8,7 @@
 LOG_FILE=$1
 
 expected_lines=(
-  "\[CORE\] Start fetching instructions"
+  "\[CORE\] Waking core via CLINT msip"
   "\[JTAG\] Halting hart 0"
   "\[JTAG\] Resumed hart 0"
   "\[UART\] Hello World!"

Bender.yml

@@ -39,6 +39,7 @@ sources:
     files:
       # Level 1
       - rtl/core_wrap.sv
+      - rtl/bootrom/bootrom.sv
       - rtl/soc_ctrl/soc_ctrl_regs.sv
       - rtl/gpio/gpio_reg_top.sv
       - rtl/gpio/gpio.sv

rtl/bootrom/bootrom.sv

@@ -0,0 +1,81 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Authors:
+// - Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+`include "common_cells/registers.svh"
+
+/// Bootrom containing a WFI trampoline.
+/// After reset the core fetches from here, enables the M-mode interrupt
+/// executes WFI, and waits until woken by CLINT msip.
+/// On wake it clears msip, reads the boot address from soc_ctrl and jumps there.
+module bootrom #(
+	/// The OBI configuration for all ports.
+	parameter obi_pkg::obi_cfg_t ObiCfg = obi_pkg::ObiDefaultConfig,
+	/// OBI request type
+	parameter type obi_req_t = logic,
+	/// OBI response type
+	parameter type obi_rsp_t = logic
+) (
+	input  logic     clk_i,
+	input  logic     rst_ni,
+	input  obi_req_t obi_req_i,
+	output obi_rsp_t obi_rsp_o
+);
+
+	// Bootrom contents (9 words, 36 bytes)
+	// https://godbolt.org/z/MP5ejvzdf
+	localparam int unsigned RomSize = 9;
+	localparam logic [31:0] RomData [RomSize] = '{
+		32'h00800293, // addi  t0, zero, 8  # t0 = 8 (MSIE bit)
+		32'h30429073, // csrw  mie, t0      # Enable M-mode software interrupt
+		32'h10500073, // wfi                # Sleep until interrupt
+		32'h020402b7, // lui   t0, 0x02040  # t0 = CLINT base (0x02040000)
+		32'h0002a023, // sw    zero, 0(t0)  # Clear msip
+		32'h30401073, // csrw  mie, zero    # Disable interrupts
+		32'h030002b7, // lui   t0, 0x03000  # t0 = SOC_CTRL base (0x03000000)
+		32'h0002a283, // lw    t0, 0(t0)    # t0 = boot address
+		32'h00028067  // jalr  zero, 0(t0)  # Jump to boot address
+	};
+
+	localparam int unsigned AddressWidth = cf_math_pkg::idx_width(RomSize) +2; // in bytes
+
+	// Handle OBI requests
+	logic                      we_d, we_q;               // delayed to the response phase
+	logic                      req_d, req_q;             // delayed to the response phase
+	logic [ObiCfg.IdWidth-1:0] id_d, id_q;               // delayed to the response phase
+	logic [AddressWidth-1:0]   read_addr_d, read_addr_q; // delayed to the response phase (word addr)
+
+	assign req_d       = obi_req_i.req;
+	assign we_d        = obi_req_i.a.we;
+	assign id_d        = obi_req_i.a.aid;
+	assign read_addr_d = obi_req_i.a.addr[AddressWidth-1:2];
+
+	// Latch request for one-cycle response
+	`FF(req_q, req_d, '0, clk_i, rst_ni)
+	`FF(we_q, we_d, '0, clk_i, rst_ni)
+	`FF(id_q, id_d, '0, clk_i, rst_ni)
+	`FF(read_addr_q, read_addr_d, '0, clk_i, rst_ni)
+
+	// Address range check
+	logic in_range;
+	assign in_range = (read_addr_q < RomSize);
+
+	always_comb begin
+		obi_rsp_o         = '0;
+		obi_rsp_o.gnt     = 1'b1; // always grant
+		obi_rsp_o.rvalid  = req_q;
+		obi_rsp_o.r.rid   = id_q;
+		if (we_q || !in_range) begin
+			// write request or out of range
+			obi_rsp_o.r.rdata = 32'hBADCAB1E;
+			obi_rsp_o.r.err   = 1'b1;
+		end else begin
+			obi_rsp_o.r.rdata = RomData[read_addr_q];
+			obi_rsp_o.r.err   = 1'b0;
+		end
+	end
+
+endmodule

rtl/croc_domain.sv

@@ -50,7 +50,6 @@ module croc_domain import croc_pkg::*; #(
   logic sram_impl; // soc_ctrl -> SRAM config signals
   logic debug_req;
   logic fetch_enable;
-  logic [31:0] boot_addr;
 
   // interrupts (irqs)
   logic clint_timer_irq;
@@ -162,6 +161,10 @@ module croc_domain import croc_pkg::*; #(
   // CLINT bus
   sbr_obi_req_t clint_obi_req;
   sbr_obi_rsp_t clint_obi_rsp;
+
+  // Bootrom bus
+  sbr_obi_req_t bootrom_obi_req;
+  sbr_obi_rsp_t bootrom_obi_rsp;
 
   // Fanout to individual peripherals
   assign error_obi_req                     = all_periph_obi_req[PeriphError];
@@ -176,8 +179,10 @@ module croc_domain import croc_pkg::*; #(
   assign all_periph_obi_rsp[PeriphGpio]    = gpio_obi_rsp;
   assign timer_obi_req                     = all_periph_obi_req[PeriphTimer];
   assign all_periph_obi_rsp[PeriphTimer]   = timer_obi_rsp;
-  assign clint_obi_req                     = all_periph_obi_req[PeriphClint];
-  assign all_periph_obi_rsp[PeriphClint]   = clint_obi_rsp;
+  assign clint_obi_req                       = all_periph_obi_req[PeriphClint];
+  assign all_periph_obi_rsp[PeriphClint]     = clint_obi_rsp;
+  assign bootrom_obi_req                     = all_periph_obi_req[PeriphBootrom];
+  assign all_periph_obi_rsp[PeriphBootrom]   = bootrom_obi_rsp;
 
 
   // -----------------
@@ -194,7 +199,7 @@ module croc_domain import croc_pkg::*; #(
     .timer_irq_i      ( clint_timer_irq    ),
     .software_irq_i   ( clint_software_irq ),
 
-    .boot_addr_i      ( boot_addr   ),
+    .boot_addr_i      ( BootromAddr ),
 
     .instr_req_o      ( core_instr_obi_req.req     ),
     .instr_gnt_i      ( core_instr_obi_rsp.gnt     ),
@@ -477,7 +482,6 @@ module croc_domain import croc_pkg::*; #(
     .rst_ni,
     .obi_req_i     ( soc_ctrl_obi_req ),
     .obi_rsp_o     ( soc_ctrl_obi_rsp ),
-    .boot_addr_o   ( boot_addr        ),
     .fetch_en_o    ( fetch_en_reg     ),
     .sram_dly_o    ( sram_impl        )
   );
@@ -555,6 +559,18 @@ module croc_domain import croc_pkg::*; #(
     .overflow_o ( ) // Not connected
   );
 
+  // Bootrom
+  bootrom #(
+    .ObiCfg    ( SbrObiCfg     ),
+    .obi_req_t ( sbr_obi_req_t ),
+    .obi_rsp_t ( sbr_obi_rsp_t )
+  ) i_bootrom (
+    .clk_i,
+    .rst_ni,
+    .obi_req_i ( bootrom_obi_req ),
+    .obi_rsp_o ( bootrom_obi_rsp )
+  );
+
   // Peripheral space error subordinate
   obi_err_sbr #(
     .ObiCfg      ( SbrObiCfg     ),

rtl/croc_pkg.sv

@@ -108,16 +108,18 @@ package croc_pkg;
     PeriphUart     = 3,
     PeriphGpio     = 4,
     PeriphTimer    = 5,
-    PeriphClint    = 6
+    PeriphBootrom  = 6,
+    PeriphClint    = 7
   } periph_outputs_e;
 
   /// Address map given to the peripheral mux
-  localparam addr_map_rule_t [5:0] periph_addr_map = '{
+  localparam addr_map_rule_t [6:0] periph_addr_map = '{
     '{ idx: PeriphDebug,   start_addr: 32'h0000_0000, end_addr: 32'h0004_0000 },
     '{ idx: PeriphSocCtrl, start_addr: 32'h0300_0000, end_addr: 32'h0300_1000 },
     '{ idx: PeriphUart,    start_addr: 32'h0300_2000, end_addr: 32'h0300_3000 },
     '{ idx: PeriphGpio,    start_addr: 32'h0300_5000, end_addr: 32'h0300_6000 },
     '{ idx: PeriphTimer,   start_addr: 32'h0300_A000, end_addr: 32'h0300_B000 },
+    '{ idx: PeriphBootrom, start_addr: 32'h0200_0000, end_addr: 32'h0200_4000 },
     '{ idx: PeriphClint,   start_addr: 32'h0204_0000, end_addr: 32'h0208_0000 }
   };
 
@@ -137,6 +139,8 @@ package croc_pkg;
     return addr;
   endfunction
 
+  localparam bit [31:0] BootromAddr  = get_periph_start_addr(PeriphBootrom);
+
 
   ///////////////////////////////////////////
   // Interconnect Types and Configurations //

rtl/soc_ctrl/soc_ctrl_regs.sv

@@ -15,7 +15,6 @@ module soc_ctrl_regs #(
   input  obi_req_t         obi_req_i,
   output obi_rsp_t         obi_rsp_o,
   // To hardware
-  output logic      [31:0] boot_addr_o,
   output logic             fetch_en_o,
   output logic             sram_dly_o
 );
@@ -44,7 +43,6 @@ module soc_ctrl_regs #(
   assign obi_req_d = obi_req_i;
 
   // Output assignment
-  assign boot_addr_o = boot_addr_q;
   assign fetch_en_o  = fetch_en_q;
   assign sram_dly_o  = sram_dly_q;
 

rtl/test/tb_croc_pkg.sv

@@ -30,4 +30,7 @@ package tb_croc_pkg;
   localparam bit [31:0] FetchEnAddr     = SocCtrlBaseAddr + soc_ctrl_regs_pkg::SOC_CTRL_FETCHEN_OFFSET;
   localparam bit [31:0] CoreStatusAddr  = SocCtrlBaseAddr + soc_ctrl_regs_pkg::SOC_CTRL_CORESTATUS_OFFSET;
 
+  // CLINT base address (msip register is at offset 0)
+  localparam bit [31:0] ClintBaseAddr   = croc_pkg::get_periph_start_addr(croc_pkg::PeriphClint);
+
 endpackage

rtl/test/tb_croc_soc.sv

@@ -134,12 +134,17 @@ module tb_croc_soc #(
 
     // write test value to sram
     i_vip.jtag_write_reg32(SramBaseAddr, 32'h1234_5678, 1'b1);
-    // load binary to sram
-    i_vip.jtag_load_hex(binary_path);
 
     $display("@%t | [CORE] Start fetching instructions", $time);
     fetch_en = 1'b1;
 
+    // load binary to sram
+    i_vip.jtag_load_hex(binary_path);
+
+    // wake core from WFI by writing to CLINT msip
+    $display("@%t | [CORE] Waking core via CLINT msip", $time);
+    i_vip.jtag_write_reg32(ClintBaseAddr, 32'h1);
+
     // halt core
     i_vip.jtag_halt();
 

verilator/croc.f

@@ -156,6 +156,7 @@
 ../rtl/clint/clint_reg_pkg.sv
 ../rtl/obi_timer/obi_timer_reg_pkg.sv
 ../rtl/core_wrap.sv
+../rtl/bootrom/bootrom.sv
 ../rtl/soc_ctrl/soc_ctrl_regs.sv
 ../rtl/gpio/gpio_reg_top.sv
 ../rtl/gpio/gpio.sv

vsim/compile_rtl.tcl

@@ -350,6 +350,7 @@ if {[catch { vlog -incr -sv \
     "+incdir+$ROOT/rtl/common_cells/include" \
     "+incdir+$ROOT/rtl/obi/include" \
     "$ROOT/rtl/core_wrap.sv" \
+    "$ROOT/rtl/bootrom/bootrom.sv" \
     "$ROOT/rtl/soc_ctrl/soc_ctrl_regs.sv" \
     "$ROOT/rtl/gpio/gpio_reg_top.sv" \
     "$ROOT/rtl/gpio/gpio.sv" \