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phsauterphsauter
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hw: configurable A_DLY SRAM pin
Documentation says it must be tied to HIGH. This was mistakenly tied low which changes the internal timings of the SRAM and can make some of them inoperable. Now it is configurable in soc_ctrl.
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10 files changed

+207
-101
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10 files changed

+207
-101
lines changed

‎Bender.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ sources:
2626
- target: ihp13
2727
files:
2828
- ihp13/tc_clk.sv
29-
- ihp13/tc_sram.sv
29+
- ihp13/tc_sram_impl.sv
3030

3131
- rtl/croc_pkg.sv
3232
- rtl/user_pkg.sv

‎croc.flist‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@ rtl/timer_unit/timer_unit_counter_presc.sv
174174
rtl/timer_unit/apb_timer_unit.sv
175175
rtl/timer_unit/timer_unit.sv
176176
ihp13/tc_clk.sv
177-
ihp13/tc_sram.sv
177+
ihp13/tc_sram_impl.sv
178178
rtl/croc_pkg.sv
179179
rtl/user_pkg.sv
180180
rtl/soc_ctrl/soc_ctrl_reg_pkg.sv

ihp13/tc_sram.sv renamed to ihp13/tc_sram_impl.sv

Lines changed: 26 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,7 @@ endmodule
2828
.A_BIST_MEN ( 1'b0 ), \
2929
.A_BIST_WEN ( 1'b0 ), \
3030
.A_BIST_REN ( 1'b0 ), \
31-
.A_BIST_EN ( 1'b0 ), \
32-
.A_DLY ( 1'b0 )
31+
.A_BIST_EN ( 1'b0 )
3332

3433
`define IHP13_TC_SRAM_256x64_TIEOFF \
3534
.A_BIST_CLK ( 1'b0 ), \
@@ -39,8 +38,7 @@ endmodule
3938
.A_BIST_MEN ( 1'b0 ), \
4039
.A_BIST_WEN ( 1'b0 ), \
4140
.A_BIST_REN ( 1'b0 ), \
42-
.A_BIST_EN ( 1'b0 ), \
43-
.A_DLY ( 1'b0 )
41+
.A_BIST_EN ( 1'b0 )
4442

4543
`define IHP13_TC_SRAM_512x64_TIEOFF \
4644
.A_BIST_CLK ( 1'b0 ), \
@@ -50,8 +48,7 @@ endmodule
5048
.A_BIST_MEN ( 1'b0 ), \
5149
.A_BIST_WEN ( 1'b0 ), \
5250
.A_BIST_REN ( 1'b0 ), \
53-
.A_BIST_EN ( 1'b0 ), \
54-
.A_DLY ( 1'b0 )
51+
.A_BIST_EN ( 1'b0 )
5552

5653
`define IHP13_TC_SRAM_1024x64_TIEOFF \
5754
.A_BIST_CLK ( 1'b0 ), \
@@ -61,8 +58,7 @@ endmodule
6158
.A_BIST_MEN ( 1'b0 ), \
6259
.A_BIST_WEN ( 1'b0 ), \
6360
.A_BIST_REN ( 1'b0 ), \
64-
.A_BIST_EN ( 1'b0 ), \
65-
.A_DLY ( 1'b0 )
61+
.A_BIST_EN ( 1'b0 )
6662

6763
`define IHP13_TC_SRAM_2048x64_TIEOFF \
6864
.A_BIST_CLK ( 1'b0 ), \
@@ -72,10 +68,9 @@ endmodule
7268
.A_BIST_MEN ( 1'b0 ), \
7369
.A_BIST_WEN ( 1'b0 ), \
7470
.A_BIST_REN ( 1'b0 ), \
75-
.A_BIST_EN ( 1'b0 ), \
76-
.A_DLY ( 1'b0 )
71+
.A_BIST_EN ( 1'b0 )
7772

78-
module tc_sram #(
73+
module tc_sram_impl #(
7974
parameter int unsigned NumWords = 32'd1024,
8075
parameter int unsigned DataWidth = 32'd128,
8176
parameter int unsigned ByteWidth = 32'd8,
@@ -84,6 +79,9 @@ module tc_sram #(
8479
parameter SimInit = "none",
8580
parameter bit PrintSimCfg = 1'b0,
8681
parameter ImplKey = "none",
82+
parameter type impl_in_t = logic,
83+
parameter type impl_out_t = logic,
84+
parameter impl_out_t ImplOutSim = 'X,
8785
// DEPENDENT PARAMETERS, DO NOT OVERWRITE!
8886
parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
8987
parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth,
@@ -93,11 +91,16 @@ module tc_sram #(
9391
) (
9492
input logic clk_i,
9593
input logic rst_ni,
94+
95+
input impl_in_t impl_i,
96+
output impl_out_t impl_o,
97+
9698
input logic [NumPorts-1:0] req_i,
9799
input logic [NumPorts-1:0] we_i,
98100
input addr_t [NumPorts-1:0] addr_i,
99101
input data_t [NumPorts-1:0] wdata_i,
100102
input be_t [NumPorts-1:0] be_i,
103+
101104
output data_t [NumPorts-1:0] rdata_o
102105
);
103106

@@ -112,6 +115,9 @@ module tc_sram #(
112115
end
113116
end
114117

118+
// We drive a static value for `impl_o` in behavioral simulation.
119+
assign impl_o = ImplOutSim;
120+
115121
// Generate desired cuts
116122
if (NumWords == 64 && DataWidth == 64 && P1L1) begin: gen_64x64xBx1
117123
logic [63:0] wdata64, rdata64, bm64;
@@ -123,6 +129,7 @@ module tc_sram #(
123129

124130
RM_IHPSG13_1P_64x64_c2_bm_bist i_cut (
125131
.A_CLK ( clk_i ),
132+
.A_DLY ( impl_i ),
126133
.A_ADDR ( addr_i [0][5:0] ),
127134
.A_BM ( bm64 ),
128135
.A_MEN ( req_i ),
@@ -142,6 +149,7 @@ module tc_sram #(
142149

143150
RM_IHPSG13_1P_256x64_c2_bm_bist i_cut (
144151
.A_CLK ( clk_i ),
152+
.A_DLY ( impl_i ),
145153
.A_ADDR ( addr_i [0][7:0] ),
146154
.A_BM ( bm64 ),
147155
.A_MEN ( req_i ),
@@ -161,6 +169,7 @@ module tc_sram #(
161169

162170
RM_IHPSG13_1P_512x64_c2_bm_bist i_cut (
163171
.A_CLK ( clk_i ),
172+
.A_DLY ( impl_i ),
164173
.A_ADDR ( addr_i [0][8:0] ),
165174
.A_BM ( bm64 ),
166175
.A_MEN ( req_i ),
@@ -180,6 +189,7 @@ module tc_sram #(
180189

181190
RM_IHPSG13_1P_1024x64_c2_bm_bist i_cut (
182191
.A_CLK ( clk_i ),
192+
.A_DLY ( impl_i ),
183193
.A_ADDR ( addr_i [0][9:0] ),
184194
.A_BM ( bm64 ),
185195
.A_MEN ( req_i ),
@@ -199,6 +209,7 @@ module tc_sram #(
199209

200210
RM_IHPSG13_1P_2048x64_c2_bm_bist i_cut (
201211
.A_CLK ( clk_i ),
212+
.A_DLY ( impl_i ),
202213
.A_ADDR ( addr_i [0][10:0] ),
203214
.A_BM ( bm64 ),
204215
.A_MEN ( req_i ),
@@ -239,6 +250,7 @@ module tc_sram #(
239250

240251
RM_IHPSG13_1P_256x64_c2_bm_bist i_cut (
241252
.A_CLK ( clk_i ),
253+
.A_DLY ( impl_i ),
242254
.A_ADDR ( addr_i [0][8:1] ),
243255
.A_BM ( bm64 ),
244256
.A_MEN ( req_i ),
@@ -280,6 +292,7 @@ module tc_sram #(
280292

281293
RM_IHPSG13_1P_512x64_c2_bm_bist i_cut (
282294
.A_CLK ( clk_i ),
295+
.A_DLY ( impl_i ),
283296
.A_ADDR ( addr_i [0][9:1] ),
284297
.A_BM ( bm64 ),
285298
.A_MEN ( req_i ),
@@ -320,6 +333,7 @@ module tc_sram #(
320333

321334
RM_IHPSG13_1P_1024x64_c2_bm_bist i_cut (
322335
.A_CLK ( clk_i ),
336+
.A_DLY ( impl_i ),
323337
.A_ADDR ( addr_i [0][10:1] ),
324338
.A_BM ( bm64 ),
325339
.A_MEN ( req_i ),
@@ -339,6 +353,7 @@ module tc_sram #(
339353

340354
RM_IHPSG13_1P_2048x64_c2_bm_bist i_cut (
341355
.A_CLK ( clk_i ),
356+
.A_DLY ( impl_i ),
342357
.A_ADDR ( addr_i [0][10:0] ),
343358
.A_BM ( bm64 ),
344359
.A_MEN ( req_i ),

‎openroad/src/instances.tcl‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,6 @@ set sram {\[0\].i_sram/}
3030
set bank0_sram0 $SRAM$sram$SRAM_512x32
3131
set sram {\[1\].i_sram/}
3232
set bank1_sram0 $SRAM$sram$SRAM_512x32
33-
set sram {\[2\].i_sram/}
34-
set bank2_sram0 $SRAM$sram$SRAM_512x32
3533

3634
set JTAG_ASYNC_REQ [get_nets $JTAG/i_dmi_cdc.i_cdc_req/*async_*]
3735
set JTAG_ASYNC_RSP [get_nets $JTAG/i_dmi_cdc.i_cdc_resp/*async_*]

‎rtl/croc_domain.sv‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ module croc_domain import croc_pkg::*; #(
4646
// -----------------
4747
// Control Signals
4848
// -----------------
49+
logic sram_impl; // soc_ctrl -> SRAM config signals
4950
logic debug_req;
5051
logic fetch_enable;
5152
logic [31:0] boot_addr;
@@ -368,7 +369,7 @@ module croc_domain import croc_pkg::*; #(
368369

369370
assign bank_word_addr = bank_byte_addr[SbrObiCfg.AddrWidth-1:2];
370371

371-
tc_sram #(
372+
tc_sram_impl #(
372373
.NumWords ( SramBankNumWords ),
373374
.DataWidth ( 32 ),
374375
.NumPorts ( 1 ),
@@ -377,6 +378,9 @@ module croc_domain import croc_pkg::*; #(
377378
.clk_i,
378379
.rst_ni,
379380

381+
.impl_i ( sram_impl ),
382+
.impl_o ( ), // not connected
383+
380384
.req_i ( bank_req ),
381385
.we_i ( bank_we ),
382386
.addr_i ( bank_word_addr ),
@@ -497,8 +501,9 @@ module croc_domain import croc_pkg::*; #(
497501

498502
soc_ctrl_reg_pkg::soc_ctrl_reg2hw_t soc_ctrl_reg2hw;
499503
soc_ctrl_reg_pkg::soc_ctrl_hw2reg_t soc_ctrl_hw2reg;
500-
assign fetch_enable = soc_ctrl_reg2hw.fetchen.q | fetch_en_i;
501-
assign boot_addr = soc_ctrl_reg2hw.bootaddr.q;
504+
assign fetch_enable = soc_ctrl_reg2hw.fetchen.q | fetch_en_i;
505+
assign boot_addr = soc_ctrl_reg2hw.bootaddr.q;
506+
assign sram_impl = soc_ctrl_reg2hw.sram_dly;
502507
assign soc_ctrl_hw2reg = '0;
503508

504509
soc_ctrl_reg_top #(

‎rtl/soc_ctrl/soc_ctrl.html‎

Lines changed: 93 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,64 +1,93 @@
1-
<!DOCTYPE html>
2-
<html>
3-
<head>
4-
<link rel=stylesheet href=reg_html.css>
5-
</head>
6-
<table class="regdef" id="Reg_bootaddr">
7-
<tr>
8-
<th class="regdef" colspan=5>
9-
<div>soc_ctrl.bootaddr @ 0x0</div>
10-
<div><p>Core Boot Address</p></div>
11-
<div>Reset default = 0x1a000000, mask 0xffffffff</div>
12-
</th>
13-
</tr>
14-
<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>bootaddr...</td>
15-
</tr>
16-
<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...bootaddr</td>
17-
</tr></table></td></tr>
18-
<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x1a000000</td><td class="regfn">bootaddr</td><td class="regde"><p>Boot Address</p></td></table>
19-
<br>
20-
<table class="regdef" id="Reg_fetchen">
21-
<tr>
22-
<th class="regdef" colspan=5>
23-
<div>soc_ctrl.fetchen @ 0x4</div>
24-
<div><p>Core Fetch Enable</p></div>
25-
<div>Reset default = 0x0, mask 0x1</div>
26-
</th>
27-
</tr>
28-
<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="unused" colspan=16>&nbsp;</td>
29-
</tr>
30-
<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="unused" colspan=15>&nbsp;</td>
31-
<td class="fname" colspan=1 style="font-size:42.857142857142854%">fetchen</td>
32-
</tr></table></td></tr>
33-
<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">0</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">fetchen</td><td class="regde"><p>Fetch Enable</p></td></table>
34-
<br>
35-
<table class="regdef" id="Reg_corestatus">
36-
<tr>
37-
<th class="regdef" colspan=5>
38-
<div>soc_ctrl.corestatus @ 0x8</div>
39-
<div><p>Core Return Status (return value, EOC)</p></div>
40-
<div>Reset default = 0x0, mask 0xffffffff</div>
41-
</th>
42-
</tr>
43-
<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>core_status...</td>
44-
</tr>
45-
<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...core_status</td>
46-
</tr></table></td></tr>
47-
<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">core_status</td><td class="regde"><p>Core Return Status (EOC(bit[31]) and status(bit[30:0]))</p></td></table>
48-
<br>
49-
<table class="regdef" id="Reg_bootmode">
50-
<tr>
51-
<th class="regdef" colspan=5>
52-
<div>soc_ctrl.bootmode @ 0xc</div>
53-
<div><p>Core Boot Mode</p></div>
54-
<div>Reset default = 0x0, mask 0x1</div>
55-
</th>
56-
</tr>
57-
<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="unused" colspan=16>&nbsp;</td>
58-
</tr>
59-
<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="unused" colspan=14>&nbsp;</td>
60-
<td class="fname" colspan=2 style="font-size:75.0%">bootmode</td>
61-
</tr></table></td></tr>
62-
<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">1:0</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">bootmode</td><td class="regde"><p>Boot Mode</p></td></table>
63-
<br>
64-
</html>
1+
## Summary
2+
3+
| Name | Offset | Length | Description |
4+
|:-------------------------------------|:---------|---------:|:---------------------------------------|
5+
| soc_ctrl.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address |
6+
| soc_ctrl.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable |
7+
| soc_ctrl.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) |
8+
| soc_ctrl.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode |
9+
| soc_ctrl.[`sram_dly`](#sram_dly) | 0x10 | 4 | SRAM A_DLY value |
10+
11+
## bootaddr
12+
Core Boot Address
13+
- Offset: `0x0`
14+
- Reset default: `0x10000000`
15+
- Reset mask: `0xffffffff`
16+
17+
### Fields
18+
19+
```wavejson
20+
{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
21+
```
22+
23+
| Bits | Type | Reset | Name | Description |
24+
|:------:|:------:|:----------:|:---------|:--------------|
25+
| 31:0 | rw | 0x10000000 | bootaddr | Boot Address |
26+
27+
## fetchen
28+
Core Fetch Enable
29+
- Offset: `0x4`
30+
- Reset default: `0x0`
31+
- Reset mask: `0x1`
32+
33+
### Fields
34+
35+
```wavejson
36+
{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
37+
```
38+
39+
| Bits | Type | Reset | Name | Description |
40+
|:------:|:------:|:-------:|:--------|:--------------|
41+
| 31:1 | | | | Reserved |
42+
| 0 | rw | 0x0 | fetchen | Fetch Enable |
43+
44+
## corestatus
45+
Core Return Status (return value, EOC)
46+
- Offset: `0x8`
47+
- Reset default: `0x0`
48+
- Reset mask: `0xffffffff`
49+
50+
### Fields
51+
52+
```wavejson
53+
{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
54+
```
55+
56+
| Bits | Type | Reset | Name | Description |
57+
|:------:|:------:|:-------:|:------------|:--------------------------------------------------------|
58+
| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) |
59+
60+
## bootmode
61+
Core Boot Mode
62+
- Offset: `0xc`
63+
- Reset default: `0x0`
64+
- Reset mask: `0x1`
65+
66+
### Fields
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```wavejson
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{"reg": [{"name": "bootmode", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
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```
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| Bits | Type | Reset | Name | Description |
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|:------:|:------:|:-------:|:---------|:--------------|
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| 31:1 | | | | Reserved |
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| 0 | rw | 0x0 | bootmode | Boot Mode |
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## sram_dly
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SRAM A_DLY value
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- Offset: `0x10`
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- Reset default: `0x1`
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- Reset mask: `0x1`
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### Fields
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```wavejson
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{"reg": [{"name": "sram_dly", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
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```
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| Bits | Type | Reset | Name | Description |
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|:------:|:------:|:-------:|:---------|:------------------------------------------------------------------|
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| 31:1 | | | | Reserved |
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| 0 | rw | 0x1 | sram_dly | Controls the A_DLY pin of the SRAMs (configured internal timings) |
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