File tree Expand file tree Collapse file tree 4 files changed +16
-6
lines changed
Expand file tree Collapse file tree 4 files changed +16
-6
lines changed Original file line number Diff line number Diff line change @@ -42,6 +42,10 @@ set input_checkpoint $::env(INPUT_CHECKPOINT)
4242utl::report " Loading checkpoint: ${input_checkpoint} "
4343load_checkpoint ${input_checkpoint}
4444
45+ # Set layers used for estimate_parasitics
46+ set_wire_rc -clock -layer Metal4
47+ set_wire_rc -signal -layer Metal4
48+
4549utl::report " ###############################################################################"
4650utl::report " # Stage 02: PLACEMENT"
4751utl::report " ###############################################################################"
@@ -53,10 +57,6 @@ utl::report "###################################################################
5357utl::report " # 02-01: Initial Repair Netlist"
5458utl::report " ###############################################################################"
5559
56- # Set layers used for estimate_parasitics
57- set_wire_rc -clock -layer Metal4
58- set_wire_rc -signal -layer Metal4
59-
6060# Don't touch clock-tree related nets as repair_timing can insert buffers
6161# which then prevents CTS from running
6262set clock_nets [get_nets -of_objects [get_pins -of_objects " *_reg" -filter " name == CLK" ]]
Original file line number Diff line number Diff line change @@ -43,6 +43,10 @@ set input_checkpoint $::env(INPUT_CHECKPOINT)
4343utl::report " Loading checkpoint: ${input_checkpoint} "
4444load_checkpoint ${input_checkpoint}
4545
46+ # Set layers used for estimate_parasitics
47+ set_wire_rc -clock -layer Metal4
48+ set_wire_rc -signal -layer Metal4
49+
4650# ##############################################################################
4751# Clock Tree Synthesis
4852# ##############################################################################
@@ -59,7 +63,6 @@ utl::report "Repair clock inverters"
5963repair_clock_inverters
6064
6165utl::report " Clock Tree Synthesis"
62- set_wire_rc -clock -layer Metal4
6366
6467# CTS buffer list (defined in init_tech.tcl)
6568# ctsBuf and ctsBufRoot are set based on PDK
@@ -73,7 +76,6 @@ set DPL_ARGS {}
7376detailed_placement {*}$DPL_ARGS
7477
7578utl::report " Estimate parasitics"
76- report_layer_rc
7779estimate_parasitics -placement
7880
7981# Propagate clocks now that we have a clock-tree
Original file line number Diff line number Diff line change @@ -43,6 +43,10 @@ set input_checkpoint $::env(INPUT_CHECKPOINT)
4343utl::report " Loading checkpoint: ${input_checkpoint} "
4444load_checkpoint ${input_checkpoint}
4545
46+ # Set layers used for estimate_parasitics
47+ set_wire_rc -clock -layer Metal4
48+ set_wire_rc -signal -layer Metal4
49+
4650utl::report " ###############################################################################"
4751utl::report " # Stage 04: ROUTING"
4852utl::report " ###############################################################################"
Original file line number Diff line number Diff line change @@ -42,6 +42,10 @@ set input_checkpoint $::env(INPUT_CHECKPOINT)
4242utl::report " Loading checkpoint: ${input_checkpoint} "
4343load_checkpoint ${input_checkpoint}
4444
45+ # Set layers used for estimate_parasitics
46+ set_wire_rc -clock -layer Metal4
47+ set_wire_rc -signal -layer Metal4
48+
4549# ##############################################################################
4650# Finishing
4751# ##############################################################################
You can’t perform that action at this time.
0 commit comments