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openroad: restore set_wire_rc after checkpoint loading
1 parent 0c5a9da commit f281159

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4 files changed

+16
-6
lines changed

4 files changed

+16
-6
lines changed

openroad/scripts/02_placement.tcl

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,10 @@ set input_checkpoint $::env(INPUT_CHECKPOINT)
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utl::report "Loading checkpoint: ${input_checkpoint}"
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load_checkpoint ${input_checkpoint}
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45+
# Set layers used for estimate_parasitics
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set_wire_rc -clock -layer Metal4
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set_wire_rc -signal -layer Metal4
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4549
utl::report "###############################################################################"
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utl::report "# Stage 02: PLACEMENT"
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utl::report "###############################################################################"
@@ -53,10 +57,6 @@ utl::report "###################################################################
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utl::report "# 02-01: Initial Repair Netlist"
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utl::report "###############################################################################"
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56-
# Set layers used for estimate_parasitics
57-
set_wire_rc -clock -layer Metal4
58-
set_wire_rc -signal -layer Metal4
59-
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# Don't touch clock-tree related nets as repair_timing can insert buffers
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# which then prevents CTS from running
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set clock_nets [get_nets -of_objects [get_pins -of_objects "*_reg" -filter "name == CLK"]]

openroad/scripts/03_cts.tcl

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,10 @@ set input_checkpoint $::env(INPUT_CHECKPOINT)
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utl::report "Loading checkpoint: ${input_checkpoint}"
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load_checkpoint ${input_checkpoint}
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46+
# Set layers used for estimate_parasitics
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set_wire_rc -clock -layer Metal4
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set_wire_rc -signal -layer Metal4
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4650
###############################################################################
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# Clock Tree Synthesis
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###############################################################################
@@ -59,7 +63,6 @@ utl::report "Repair clock inverters"
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repair_clock_inverters
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utl::report "Clock Tree Synthesis"
62-
set_wire_rc -clock -layer Metal4
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# CTS buffer list (defined in init_tech.tcl)
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# ctsBuf and ctsBufRoot are set based on PDK
@@ -73,7 +76,6 @@ set DPL_ARGS {}
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detailed_placement {*}$DPL_ARGS
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utl::report "Estimate parasitics"
76-
report_layer_rc
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estimate_parasitics -placement
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# Propagate clocks now that we have a clock-tree

openroad/scripts/04_routing.tcl

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,10 @@ set input_checkpoint $::env(INPUT_CHECKPOINT)
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utl::report "Loading checkpoint: ${input_checkpoint}"
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load_checkpoint ${input_checkpoint}
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46+
# Set layers used for estimate_parasitics
47+
set_wire_rc -clock -layer Metal4
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set_wire_rc -signal -layer Metal4
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utl::report "###############################################################################"
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utl::report "# Stage 04: ROUTING"
4852
utl::report "###############################################################################"

openroad/scripts/05_finishing.tcl

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,10 @@ set input_checkpoint $::env(INPUT_CHECKPOINT)
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utl::report "Loading checkpoint: ${input_checkpoint}"
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load_checkpoint ${input_checkpoint}
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45+
# Set layers used for estimate_parasitics
46+
set_wire_rc -clock -layer Metal4
47+
set_wire_rc -signal -layer Metal4
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4549
###############################################################################
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# Finishing
4751
###############################################################################

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